Testability Analysis Research Articles

Testability analysis based on the identification of testable blocks with predefined properties

The paper presents testability analysis method that is based on partitioning circuit under analysis (CUA) into testable blocks (TBs). The concept of TBs is further utilized for power consumption reduction during the test application. Software tools which were developed during the research and integrated into the third party design flow are also described. The experimental results gained from the application of the methodology on selected benchmarks and practical designs are demonstrated. It was proven on the benchmarks, used for the verification of the methodology, that a fault coverage comparable to the partial scan method can be obtained. When combined with test vectors/scan cells reordering methodology significant power savings can be reached.

A Method for the Automatic Selection of Test Frequencies in Analog Fault Diagnosis

A new procedure for the selection of test frequencies in the parametric fault diagnosis of analog circuits is presented. It is based on the evaluation of algebraic indices, as the condition number and the norm of the inverse, of a sensitivity matrix of the circuit under test. This matrix is obtained starting from the testability analysis of the circuit. A test index (T.I.) that permits the selection of the set of frequencies that better leads to locating parametric faults in analog circuits is defined. By exploiting symbolic analysis techniques, a program that implements the proposed procedure has been developed. It yields the requested set of frequencies by means of an optimization procedure based on a genetic algorithm that minimizes the T.I. Examples of the application of the proposed procedure are also included.

Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems

This paper presents the design, layout, and testability analysis of delay-insensitive circuits on cellular arrays for nanocomputing system design. In delay-insensitive circuits the delay on a signal path does not affect the correctness of circuit behavior. The combination of delay-insensitive circuit style and cellular arrays is a useful step to implement nanocomputing systems. In the approach proposed in this paper the circuit expressions corresponding to a design are first converted into Reed---Muller forms and then implemented using delay-insensitive Reed---Muller cells. The design and layout of the Reed---Muller cell using primitives has been described in detail. The effects of stuck-at faults in both delay-insensitive primitives and gates have been analyzed. Since circuits implemented in Reed---Muller forms constructed by the Reed---Muller cells can be easily tested offline, the proposed approach for delay-insensitive circuit design improves a circuit's testability. Potential physical implementation of cellular arrays and its area overhead are also discussed.

Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units

High-speed datapaths in microprocessors and embedded processors contain complex floating-point (FP) arithmetic units which have a critical role in the processor's performance. Although the FP units' complex structure consists of classic integer arithmetic components, the embedded components encounter serious testability problems due to their limited accessibility from the FP unit ports and testability loss due to FP unit inherent operations, such as rounding and normalization. In this paper, we analyze the testability problems and present scalable test generation for FP units using as a demonstration vehicle the popular, high-speed, two-path architecture of the most complex unit, the FP adder. The key feature of the presented methodology is the identification of testability conditions that guarantee effective test pattern application and fault propagation for each of the components of the FP adder. The identified test conditions can be utilized with respect to any fault model and are independent of the internal structure and the size of the components. Thus, they can be applied to FP adders of various exponent and significant sizes (single, double, and custom precision), as well as to other types of FP units, which also consist of classic integer arithmetic components similarly interconnected

System Testability Analysis for Complex Electronic Devices Based on Multisignal Model

It is necessary to consider the system testability problems for electronic devices during their early design phase because modern electronic devices become smaller and more compositive while their function and structure are more complex. Multisignal model, combining advantage of structure model and dependency model, is used to describe the fault dependency relationship for the complex electronic devices, and the main testability indexes (including optimal test program, fault detection rate, fault isolation rate, etc.) to evaluate testability and corresponding algorithms are given. The system testability analysis process is illustrated for USB-GPIB interface circuit with TEAMS toolbox. The experiment results show that the modelling method is simple, the computation speed is rapid and this method has important significance to improve diagnostic capability for complex electronic devices.

Fault Diagnosis in Analog Circuits Based on Testability Analysis and Multi-Frequency TPG Using Neural Networks

Fault Diagnosis in Analog Circuits Based on Testability Analysis and Multi-Frequency TPG Using Neural Networks

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. The advantage of the approach lies in its practicality since it uses conventional ATPG and it automatically benefits from advances in the field. Experiments on ISCAS’85 and full-scan ISCAS’89 circuits demonstrate the competitiveness of the method and measure the performance of simulation for fault equivalence.

A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead

This paper describes a built-in self-test (BIST) hardware overhead minimization technique used during a BIST synthesis process. The technique inserts a minimal amount of BIST resources into a digital system to make it fully testable. The BIST resource insertion is guided by the results of symbolic testability analysis. It takes into consideration both BIST register cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealing algorithm is used to solve the overhead minimization problem. Experiments show that considering wiring area during BIST synthesis results in smaller final designs as compared to the cases when the wiring impact is ignored.

Fault characterisation and testability issues of complementary pass transistor logic circuits

Testability of basic and complex logic gates employing complementary pass transistor logic (CPL) circuits under various single stuck faults has been investigated. Results show that all stuck-on faults, bridging faults and more than 90% of stuck-at faults in basic CPL gates are detectable only by current monitoring, generally known as IDDQ testing. It is also shown that all stuck-open faults in the basic CPL gates are detectable only by logic monitoring using an appropriate two-pattern test. Testability analysis of a CPL full-adder under a single stuck-on fault condition shows that stuck-on faults on all MOS transistors of the SUM logic and the CARRY logic circuit can be detected by signal source current monitoring with appropriate test vectors. Similarly, stuck-at faults on all MOS transistors of the full-adder can be detected by current monitoring only, and stuck-open faults on all MOS transistors of the full-adder can be detected by an appropriate two-pattern test. It is concluded that signal source current monitoring (IDDQ testing) is the best method for fault detection in CPL circuits, and gives more than 94% fault coverage of stuck-at, stuck-on and bridging faults; and logic monitoring gives 100% fault coverage of stuck-open faults.

Testability Analysis of Data-Flow Software

This paper is about testability analysis for data-flow software. We describe an application of the SATAN method, which allows testability of data-flow designs to be measured, to analyze testability of the source code of critical data-flow software, such as avionics software. We first propose the transformation of the source code generated from data-flow designs into the Static Single Assignment (SSA) form; then we describe the algorithm to automatically translate the SSA form into a testability model. Thus, analyzing the testability model can allow the detection of the software parts which induce a testability weakness.

Neural network-based analog fault diagnosis using testability analysis

A fault diagnosis procedure for analog linear circuits is presented. It uses an off-line trained neural network as a classifier. The innovative aspect of the proposed approach is the way the information provided by testability and ambiguity group determination is exploited when choosing the neural network architecture. The effectiveness of the proposed approach is shown by comparing with similar work that has already appeared in the literature.

Testability-analysis driven test-generation of analogue cores

A new definition of the testability transfer factor for circuit components that provides better sensitivity with respect to parametric deviations is presented. New equations for the testability measures in a mixed-signal core are given. Testability analysis is used for test-pattern generation and for consideration of inserting wrapper cells. The simulation results show the effectiveness of the approach.

Nested Loops Degree Impact on RTL Digital Circuit Testability

The existence of loops in a circuit structure causes problems in both test generation and application. Thus, the problem of identifying loops becomes an important task during testability analysis or, later, e.g., during allocation-for testability process. When nested loops occur in the circuit, it is necessary to accurately determine the most nested one to improve circuit testability significantly, with minimal design cost. This paper deals with the problem of identifying nested loops including their nesting degree in the register-transfer level (RTL) digital circuit structure as well as with the impact of such loops on the circuit testability.

Test synthesis of systems-on-a-chip

Embedded systems are increasingly synthesized today as systems-on-a-chip (SOCs), wherein existing functional blocks (also called cores) are used to implement different functions in the system specification. Emphasis during system synthesis is usually on optimizing one or more objectives such as price, area, performance and power. Testability enhancement of the SOC solution so obtained follows as a postprocessing step to enable the application of precomputed test sequences to each embedded core and observe its responses. Unfortunately, performing test modifications after the SOC design has been optimized for target design constraints does not preserve the optimality of the solution obtained. In this paper, the authors present the first system-level synthesis for testability framework that integrates testability considerations into the synthesis process. Their work incorporates finite-state automata (FSA)-based symbolic testability analysis within the framework of an existing multiobjective optimization-based system synthesis tool to provide a viable solution. The experimental results show that the use of FSA-based testability analysis facilitates low test overheads and test application times without sacrificing the test coverage of the embedded cores. System synthesis through the integrated framework for a number of examples indicates that efficient SOC architectures, which tradeoff different architectural features such as integrated circuit price, power consumption, and area under real-time constraints, can now be easily generated with low testability costs.

Multilevel testability analysis and solutions for integrated Bluetooth transceivers

As use of wireless communications rises and profit margins shrink, low-cost solutions are becoming increasingly important. Incorporating test design and DFT into the system design flow is essential to achieving such solutions. This case study analyzes test requirements, implications, and test cost for low-cost Bluetooth systems, which enable communication among several electronic components.

A comprehensive approach to the partial scan problem using implicit state enumeration

This paper presents a novel technique to evaluate the noncontrollability measures of state registers for partial scan design. Our model uses implicit techniques for finite state machine (FSM) traversal to identify noncontrollable state registers. By implicitly enumerating the states of a machine, we accurately evaluate the noncontrollability of flip-flops by determining exactly what values can or cannot be stored or are difficult to store in the state registers. By doing so, we not only target the untestable faults due to state unreachability of the machine but also the difficult-to-test faults caused by difficult-to-control flip-flops. The values observed in the flip-flops during the implicit FSM traversal are used to evaluate flip-flop controllability measures to support the testability analysis. This technique is programmed as an algorithm called SIMPSON and the authors analyze its effectiveness by carrying out extensive experiments over a large set of MCNC and ISCAS benchmarks. For large circuits, implicit state enumeration becomes infeasible because of computer memory and time limitations. To overcome these limitations, we propose the use of approximate reachability analysis of the circuit to estimate the noncontrollability of state registers. By partitioning a large FSM into smaller sub-FSMs, and implicitly traversing the individual submachines, the reachable state set can be overapproximated as a product of smaller subsets. The values observed in the flip-flops of the submachines during the approximate FSM traversal facilitates the estimation of their noncontrollability measures. An algorithm called SAMSON is proposed for this purpose and its effectiveness is illustrated over some of the larger circuits in the ISCAS benchmark suite. The results demonstrate the superiority of the authors' method over conventional state-of-the-art scan register selection techniques in terms of higher fault coverage achieved by selecting fewer, or an equal number, of partial scan registers.

Behavioral-Level DFT via Formal Operator Testability Measures

The focus of this research is on the testability analysis of the operators in the behavioral description prior to synthesis. The controllabilities of the inputs to an operator and the observabilities of the outputs of the operation are computed from the value ranges of the variables that serve as the inputs and outputs. Candidate hard-to-test operations are selected for testability enhancement based on the computed testability measures for all the involved operations in the behavioral description. While value ranges have been applied to compute variable testability measures, this paper addresses computation of the operator testability. Experimental results show that circuits synthesized using our technique exhibit higher testability than variable selection while keeping the area-performance overhead to a minimum.

Diagnosis Strategies for Hardware or Software Systems

In this paper we explore two alternative approaches to system diagnosis. The first strategy is based on testability analysis performed by SATAN tool. The second approach performed by the Sequential Diagnosis Tool (SDT) generates solutions with minimum average cost of the diagnostic tree. The application of either approach in practice depends on the goals, constraints and the available system test data. The SATAN approach is suitable for the cases where the system structure (i.e., interconnection of its functional parts) is given, while in the second approach the probabilities of faulty states and the test matrix implicitly describe the functionality of the diagnosed system.

TAO: regular expression-based register-transfer level testability analysis and optimization

In this paper, we present testability analysis and optimization (TAO), a novel methodology for register-transfer level (RTL) testability analysis and optimization of RTL controller/data path circuits. Unlike existing high-level testing techniques that cater restrictively to certain classes of circuits or design styles, TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circuits including application-specific integrated circuits (ASICs), application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. We also augment TAO with a design-for-test (DFT) framework that can provide a low-cost testability solution by examining the tradeoffs in choosing from a diverse array of testability modifications like partial scan or test multiplexer insertion in different parts of the circuit. Test generation is symbolic and, hence, independent of bit width. Experimental results on benchmark circuits show that TAO is very efficient, in addition to being comprehensive. The fault coverage obtained is above 99% in all cases. The average area and delay overheads for incorporating testability into the benchmarks are only 3.2% and 1.0%, respectively. The test generation time is two-to-four orders of magnitude smaller than that associated with gate-level sequential test generators, while the test application times are comparable.

Testability analysis in communicating systems

Efficiency of communication software depends on the testability of the Implementation Under Test, and consequently testability must be analyzed at the design step. Design For Testability increases in complexity when the concern is on Testing Through an Environment. Early work by the first author demonstrated the benefits and potential of Refusal Graphs as a formalism to analyze testability. The formal model of the system to be implemented possibly contains internal loops that create divergence and negatively influence the analysis's accuracy. In practice, such a problem arises in situations of Testing Through an Environment where (i) the global specification is obtained by composition of elementary behaviors, and (ii) part of the communications cannot be observed. In the paper, enhanced refusal graphs with divergence are introduced to handle the divergence problem for testability analysis including systems whose communications remain partly unobservable. Two notions, Conformance Through an Environment and Degradation of Testability, are formally introduced for Testing Through an Environment. The testability analysis algorithm has been implemented in a prototype written in C.