Abstract
A digital circuit includes two main parts: a controller and a datapath. After connection of these two parts, both are subject to a sharp fall in testability due to the lack of controllability and observability at the interface. In this paper, we propose a method for specifying the control part in order to restore the testability of the datapath to a level close to the initial one, in other words its testability before connection. This testability driven specification affects the next state logic as well as the decoder part of the controller but does not make use of any scan‐based element. Based on the finite automata theory and on results of a testability analysis performed on the datapath, the proposed method entails very little area penalty.
Highlights
Most of digital circuits are composed of a datapath and of a controller (Fig. 1)
While the proposed method targets testability improvement of the datapath only, the results reported in Table III concerning the faults in the controller show that it improves a lot the testability of the whole circuit
The command words and transitions to add are the results of one test path for each module obtained from the datapath register transfer (RT) level testability analysis
Summary
Most of digital circuits are composed of a datapath and of a controller (Fig. 1). This dichotomy is apparent when the circuit is obtained through a HighLevel Synthesis flow. The controller sequences the normal flow of execution of the datapath. Even if the datapath is fully testable when considered in isolation, if generated using a High Level Synthesis for Testability tool [1,2] for a survey), its testability can be strongly affected after connection to the control part. The controller implements only the normal flow of execution. As a consequence, (1) the actual set of control words and (2) the word sequencing in system mode may limit the possibilities of faults testing in the datapath
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