SCOAP-based Testability Analysis from Hierarchical Netlists

C P Ravikumar,H Joshi

doi:10.1155/1998/32654

C P Ravikumar, H Joshi

Open Access

https://doi.org/10.1155/1998/32654

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Abstract

Circuits of VLSI complexity are designed using modules such as adders, multipliers, register files, memories, multiplexers, and busses. During the high-level design of such a circuit, it is important to be able to consider several alternative designs and compare them on counts of area, performance, and testability. While tools exist for area and delay estimation of module-level circuits, most of the testability analysis tools work on gate-level descriptions of the circuit. Thus an expensive operation of flattening the circuit becomes necessary to carry out testability analysis. In this paper, we describe a time and space-efficient technique for evaluating the well known SCOAP testability measure of a circuit from its hierarchical description with two or more levels of hierarchy. We introduce the notion of SCOAP Expression Diagrams for functional modules, which can be precomputed and stored as part of the module data base. Our hierarchical testability analysis program, HISCOAP, reads the SCOAP expression diagrams for the modules used in the circuit, and evaluates the SCOAP measure in a systematic manner. The program has been implemented on a Sun/SPARC workstation, and we present results on several benchmark circuits, both combinational and sequential. We show that our algorithm also has a straightforward parallel realization.

Highlights

Testability-driven synthesis of digital systems requires a method to measure the testability of a circuit given its structural description
We describe HISCOAP-a hierarchical implementation of SCOAP that operates on a hierarchical netlist description of the circuit
We have presented a hierarchical implementation of the well known SCOAP testability analysis program

Summary

INTRODUCTION

Testability-driven synthesis of digital systems requires a method to measure the testability of a circuit given its structural description. Present work on testability-driven synthesis uses simple measures for testability, such as the number of self-loops in the structure graph of the circuit. The partial scan design problem is to determine the smallest subset of flip-flops which, when scanned, would give the maximum fault coverage; the SCOAP measure of the scanned circuit gives a good estimate of this fault coverage. Techniques such as Simulated Annealing [8] and Genetic Algorithms [7] have been used for solving the scan selection problem.

SCOAP FOR MODULAR CIRCUITS

SCOAP Expression Diagrams for Combinational Circuits

SED for Observability Calculation

Sequential Circuits

Storage Requirements

CONCLUSIONS