Test Pattern Generation Research Articles

Fuzzy logic based Truly Random number generator for high-speed BIST applications

Communication security is a major concern in the developed world. A key feature of security is the facility to detect the person on the other side of communication with almost 100% inevitability. This concern can be disabled by using the random number generators, that generating exclusive identities for each person in a network. The same random number generators find application in the field of testing to apply test patterns for the circuit under test. One such method is proposed here. The proposed work is the implementation of three ring oscillator based truly random number generators with application of fuzzy logic concept. The randomness from this type of generator instigates from phase noise in a ring oscillator. The proposed fuzzy based random number generators were intended to ensure a low slew rate at the inverter switching threshold. The output of the proposed system depicts a great increase in timing compared to the existing design. The ring oscillator based Truly Random Generator is used as a Test pattern generator in Built in Self Test (BIST) applications and the results are compared with other existing approaches.

Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits

Due to their shrinking feature sizes as well as environmental influences, such as high-energy radiation, electrical noise, and particle strikes, integrated circuits are getting more vulnerable to transient faults. Accordingly, how to make those circuits more robust has become an essential step in today’s design flows. Methods increasing the robustness of circuits against these faults already exist for a long period of time but either introduce huge additional logic, change the timing behavior of the circuit, or are applicable for dedicated circuits such as microprocessors only. In this paper, we propose an alternative method, which overcomes these drawbacks by determining application-specific knowledge of the circuit, namely the relations of flip-flops and when they assume the same value. By this, we exploit partial redundancies, which are inherent in most circuits anyway (even the optimized ones), to frequently compare the circuit signals for their correctness—eventually leading to an increased robustness. Since determining the correspondingly needed information is a computationally hard task, formal methods, such as bounded model checking, satisfiability-based automatic test pattern generation, and binary decision diagrams, are utilized for this purpose. The resulting methodology requires only a slight increase in additional hardware, does only influence the timing behavior of the circuit negligibly, and is automatically applicable to arbitrary circuits. Experimental evaluations confirm these benefits.

Low Cost Test Pattern Generation in Scan-Based BIST Schemes

This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.

Automatic Test Pattern Generation Through Boolean Satisfiability for Testing Bridging Faults

Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults.

Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors

Generating functional tests for processors has been a challenging problem for decades in the very large-scale integration testing field. This paper presents a method that generates software-based self-tests by leveraging bounded model checking (BMC) techniques and targeting, for the first time, out-of-order [out-of-order execution (OOE)] superscalar processors. To combat the state-space explosion associated with BMC, the proposed method starts by combining module-level abstraction-refinement with slicing to reduce the size of the model under verification. Next, an off-the-shelf BMC solver is used on the obtained extended finite-state machines to generate the leading sequences that are necessary to excite internal processor functions. Finally, constrained automatic test-pattern generation is used to cover all structural faults within every function excited by the obtained leading sequences. Experimental results show that the proposed method leads to extremely high fault coverage on the critical components corresponding to OOE operations in functional mode. The method therefore helps in tackling the over-testing problem that is inherent to the full-scan test approach.

P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings

According to the prior research, a deterministic parallel test pattern generation (TPG) engine was realized and generated the same test pattern set the serial automatic test pattern generation does during acceleration. However, for retaining the determinism, tremendous idle time is observed when different tasks (either dependent or independent) were synchronized among threads. Therefore, a new deterministic parallel TPG engine called P4-TPG is developed and incorporates preemptive, proactive, and preventive schedulings to further save/reuse the idle time during acceleration. In P4-TPG, preemptive scheduling first modifies the thread flow and brings forward, as many latter tasks as possible, to the idle time. Next, proactive scheduling inserts prospective TPG tasks of unprocessed faults to the remaining idle time and increases the overall utilization of threads. Last, preventive scheduling dynamically skips faults incompatible with the working pattern per thread and shortens the fault list during fault compaction. The experimental results show that P4-TPG not only generates the same test pattern set as the serial TPG does but also achieves averagely $10.36\times $ speedups, is 96.6% better than the prior research, using 12 threads on 18 benchmark circuits.

An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST

In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

Multiple Controlled Antirandom Testing (MCAT) for High Fault Coverage in a Black Box Environment

Among the black-box approaches to digital circuit testing, Random testing is popular due to its simplicity and cost effectiveness. Unfortunately, available evidences suggest that Random testing is equipped with a number of redundant patterns that increase test length without significantly raising the fault coverage. An extension to Random testing is Antirandom that removes redundancy by introducing a divergent pattern with every subsequent test pattern selection. A divergent pattern is induced by maximizing the Hamming distance and Cartesian distance of every subsequent test pattern from the set of previously applied test patterns. However, an enumeration of input combinations is required for the selection of a divergent pattern. Therefore, selection of a divergent pattern from all input combinations restricts the scalability of an Antirandom test pattern generation. One of the recently considered approaches is the stacking of locally optimized short sequences to generate a complete test sequence. Locally optimized short sequences originate from randomly chosen patterns instead of divergent patterns to avoid enumeration of input space. Seeding of random patterns for short sequences affects global diversity of the generated test sequence and hence, fault coverage is compromised. Therefore, this paper firstly proposes a tree traversal search based selection of divergent patterns that eliminates the search space. Ease in divergent pattern selection is used to generate optimal short sequences for divergent patterns instead of random patterns. Consequently, Multiple Controlled Antirandom Tests (MCATs) are generated that maximize distance between locally optimal short sequences to elevate the fault coverage. Fault simulation results on both ISCAS’85 and ISCAS’89 benchmark circuits prove the scalability and effectiveness of the proposed approach. Moreover, the comparison shows that up to 12% of fault coverage is improved as a result of proposed MCAT test pattern generation.

A Low-Cost Self-Test Architecture Integrated With PRESENT Cipher Core

Cryptographic cores integrated with self-test ability fulfill both data security and reliability requirements of the Internet of Things (IoT) network. However, from the IoT perspective where most devices are resource constrained, a fundamental problem associated with most of the self-test architectures is high hardware overhead due to the additional circuit for self-test operation. This paper presents the design of a low-cost self-test architecture and its integration with the PRESENT cipher core. The hardware overhead of the proposed low-cost self-test architecture is reduced by adopting two key strategies: 1) using hardware-efficient X-Compactor technique for test response compaction and 2) reusing the PRESENT cipher core as a Test Pattern Generator (TPG). The proposed self-test architecture is implemented on different Xilinx Field Programmable Gate Array (FPGA) platforms and devices. Analysis of the implementation results shows that the proposed self-test method occupies 23% less hardware area overhead and provides 14% higher throughput per slice performance with the fault coverage of over 99% compared with the existing self-test designs. The resulting analysis indicates that the proposed self-test design is one of the most viable testing solutions for resource-constrained IoT devices.

DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG

Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests for single stuck-at faults. DR-scan is able to test memory elements in dual-rail logic without breaking local feedback loops. To reduce test time, we choose a minimum set of selected test configurations (TCs). If there are more than one selected TCs, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our test methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve test coverage up to nearly 94% for various asynchronous circuits.

A Specification-Based Semi-Formal Functional Verification Method by a Stage Transition Graph Model

The semi-formal verification method, in which the functionality is formally specified and the checking is undertaken through the formal model-based simulation, has been a promising choice for the functional verification of hardware designs. The existing methods derive the formal model from design implementation. This causes poor scalability and practicality. A more feasible solution is to derive the formal model directly from the specification. In this paper, we propose a specification-based semi-formal method for functional verification. The proposed semi-formal method uses a stage transition graph (STG) model to formally describe the function points in the specification. Meanwhile, we propose an automatic test pattern generation (ATPG) method to generate the test vectors based on the STG model. The proposed STG-based ATPG method can reach possible corner cases and ensure exhaustive exploration of functionality for both control-dominated designs and data-dominated designs. Moreover, we develop an STG-based tool for automatic verification. Our experiments show that our method can automatically verify the functional correctness from the specification while achieving similar code coverage as implementation-based semi-formal approaches.

A Test Pattern Generation Technique for Approximate Circuits Based on an ILP-Formulated Pattern Selection Procedure

Intrinsic resiliency of many today's applications opens new design opportunities. Some computation accuracy loss within the so-called resilient kernels does not affect the global quality of results. This has led the scientific community to introduce the approximate computing paradigm that exploits such a concept to boost computing system performances. By applying approximation to different layers, it is possible to design more efficient systems—in terms of energy, area, and performance—at the cost of a slight accuracy loss. In particular, at hardware level, this led to approximate integrated circuits. From the test perspective, this particular class of integrated circuits leads to new challenges. On the other hand, it also offers the opportunity of relaxing test constraints at the cost of a careful selection of so-called approximation-redundant faults . Such faults are classified as tolerable because of the slight introduced error. It follows that improvements in yield and test-cost reduction can be achieved. Nevertheless, conventional automatic test pattern generation (ATPG) algorithms, when not aware of the introduced approximation, generate test vectors covering approximation-redundant faults, thus reducing the yield gain. In this work, we show experimental evidence of such problem and present a novel ATPG technique to deal with it. Then, we extensively evaluate the proposed technique, and show that we are able to achieve an average yield improvement ranging from 19% up to 36% — compared to conventional ATPG—in terms of approximation-redundant fault coverage reduction. In some cases, the improvement can reach up to 100%.

Clock-Less DFT-Less Test Strategy for Null Convention Logic

Null Convention Logic (NCL) is a robust asynchronous technique that poses new challenges to test and testability strategies due to the lack of a clock signal and the state-holding behavior of the NCL gates. The lack of deterministic timing in NCL complicates the management of test timing, and stuck-at faults on gate internal feedback (GIF) of the NCL gates exhibit a totally different effect compared to that of stuck-at faults on the gate inputs. Stuck-at faults on gate internal feedback of NCL gates do not always cause an incorrect output and therefore are considered hard-to-detect or undetectable by automatic test pattern generation (ATPG) algorithms. Such faults could leave the primary outputs of the circuit completely unaffected or sometimes they only affect the circuit by early detection of completeness. This work first proposes a clock-less self-timed ATPG, with no added design for test (DFT), that detects all of the faults on the gate inputs and a share of those on the GIF of gates. Then, this work investigates the effectiveness of I_DDQ (quiescent current) test for detecting stuck-at faults on GIF of NCL gates. Hspice is used for implementing static and semi-static transistor-level NCL gates in (45 nm, 1.1 V) technology, for which the supply current is measured and compared for fault-free and faulty circuits. The experimental results show that the faulty current is orders of magnitude higher than the fault-free leakage current. This considerable difference shows that I_DDQ testing might be an efficient and low-cost candidate for detecting stuck-at faults on GIF of NCL gates. The proposed I_DDQ test method along with the self-timed ATPG has resulted in average 98.16 and 98.04 percent fault coverage for static and semi-static implementations of several NCL circuits, respectively. To the extent of our knowledge, this is the first work that has addressed clock-less, self-timed ATPG for NCL with no area overhead, and also the first work conducted on I_DDQ test for NCL.

On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits

Opens are known to be one of the predominant defects in nanoscale technologies. With an increasing number of complex cells in today’s very large-scale integration designs intracell opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOFs) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. Furthermore, generated tests might be invalidated in case hazards and charge-sharing are not properly considered. In this paper, we present a waveform-accurate SAT-based automatic test pattern generation (ATPG) framework to tackle these problems. The proposed method not only allows for the generation of tests that are robust against hazards and charge-sharing, it can also be used to generate tests for faults only detectable by hazard-based activation—and hence even increase the fault coverage beyond state-of-the-art cell-aware tests. Our experimental results for the largest ITC’99, IWLS 2005 as well as larger industrial circuits mapped to the state-of-the-art NanGate 45-nm as well as NanGate 15-nm cell library using complex cells show the high efficiency and scalability of the proposed method. For example, the results show that without properly considering hazards and charge-sharing up to 17.9% of the generated tests could be invalidated. In addition, hazard-activated ATPG allows to detect an additional 10.1% of conventionally undetectable faults that could result in a very significant defective parts per million improvement.

Toward a New Methodology for an Efficient Test of Reconfigurable Hardware Systems

This paper deals with the test of a reconfigurable hardware system (RHS). The latter is a hardware device that allows to change the hardware resources at runtime in order to modify the system functions and therefore to dynamically adapt the system to its environment. The increasing functional complexity of embedded systems and the transition to the RHS make the hardware testing a challenging task, especially under the confine of providing a high quality with a low cost. Considering the fact that the hardware test represents a key cost factor in a production process, an optimal test strategy can be advantageous in the competitive industrial market. Accordingly, this paper introduces a new methodology for an efficient hardware test of RHS. For an RHS, the number of stuck-at faults can be very large, which leads to a significant slowdown in the testing process. Because of the redundancy of faults between the different circuits composing an RHS, the proposed methodology aims at minimizing the number of faults using the inter-circuits relationships and consequently at providing an optimal fault set that can be effectively used for testing. Efficient techniques for test generation and test set validation are proposed to provide the test patterns for faults reduced by inter-circuits fault collapsing. The application of the generated test patterns is typically sufficient to provide an overall fault coverage. The proposed methodology is implemented in a new visual environment named TnTest. An experimental study confirms and validates the expected findings. Note to Practitioners —This paper addresses possible challenges for future generations of adaptive embedded systems. It proposes an original methodology for an efficient reconfigurable hardware system (RHS) hardware test. The main objective is to significantly reduce time and cost needed for the testing process. For an RHS, the number of stuck-at faults can be very large, which can cause a major slowdown in the hardware test. Based on the inter-circuits relations existing between the different circuits composing an RHS, the proposed methodology decreases considerably not only the number of the faults but also the test patterns needed for testing. The application of the generated test patterns is typically sufficient to provide an overall fault coverage. The proposed methodology is implemented in a new visual software environment named TnTest, which is capable of providing the smallest fault set as well as the efficient test set that can be effectively used for testing. This environment can be applied to test any embedded device that can be deployed in any new application based on flexible technologies. It can also be useful in manufacturing industries for a required improvement of the production process in relation to time and cost.

A Mixture between Rule 90 and Rule 150 Cellular Automata as a Test Pattern Generator

A Mixture between Rule 90 and Rule 150 Cellular Automata as a Test Pattern Generator

An ADC BIST using on-chip ramp generation and digital ORA

This paper presents an on-chip built-in self-test technique for testing an ADC. The conventional test of a mixed signal element has performed through DSP based tester with the help of an arbitrary waveform and a signal digitizer but it is consuming more time and cost. Hence, the testing strategy has started an on-chip BIST based testing scheme to control the testing issues. An on-chip ramp generator based BIST technique has proposed for testing static characteristics of ADC. The evaluation procedure of this BIST consists of test pattern generation and output response analysis. A novel cascode current mirror based analog linear ramp generator has used to generate the test pattern through fast switching TIQ comparator based ADC. Output response analyzer evaluates switching positions of binary code for computing the static parameters. The proposed ADC BIST has implemented in 0.18 μm technology with the supply voltage of 1.8 V.

Complex automotive ICs defect localization driven by quiescent power supply current: Three cases study

Quiescent current (IDDQ) test demonstrated over years its effectiveness in identifying the ICs failure root causes. In this paper three cases study are presented, all based on the use of IDDQ test during Emission Microscopy (EMMI). The DUTs analyzed, implemented in different technological solutions (BCD and BiCMOS), belong to the automotive market segment. In the cases here described the emission microscopy approach from both front and backside has been considered. Different physical analysis techniques have been used in order to characterize morphological marginalities or abnormalities. Results from the three cases should be good examples to prove how this kind of approach - fault isolation driven by IDDQ - is a powerful technique able to identify quickly and precisely failure root causes in high complexity ICs, independently of design and technology, and even when Automatic Test Pattern Generation (ATPG) is not available.Preferred presentation:[] Oral.[] Poster.[X] No preference.Preferred track (please, tick one or number 1 to 3 tracks in order of preference: 1 = most suiting, 3 = least suiting).[3]A - Quality and Reliability Assessment Techniques and Methods for Devices and Systems[] B1 - Si Technologies & Nanoelectronics: Hot Carriers, High K, Gate Materials[] B2 - Si Technologies & Nanoelectronics: Low K, Cu Interconnects[] B3 - Si Technologies & Nanoelectronics: ESD, Latch-up[1]C - Progress in Failure Analysis: Defect Detection and Analysis[] D - Reliability of Microwave and Compound Semiconductors Devices[2]E1 - Power Devices Reliability: Silicon and Passive[] E2 - Power Devices Reliability: Wide Bandgap Devices[] F - Packaging and Assembly Reliability[] G - MEMS, Sensors and Organic Electronics Reliability[] H - Photonics Reliability[] I - Extreme Environments and Radiation[] K - Renewable Energies Reliability[] L - Modeling for Reliability[] SS1 (Special Session) - Reliability in Traction Applications

An Efficient Technique to Reverse Engineer Minterm Protection Based Camouflaged Circuit

Integrated circuit (IC) camouflaging technique has been applied as a countermeasure against reverse engineering (RE). However, its effectiveness is threatened by a boolean satisfiability (SAT) based de-camouflaging attack, which is able to restore the camouflaged circuit within only minutes. As a defense to the SAT-based de-camouflaging attack, a brand new camouflaging strategy (called CamoPerturb) has been proposed recently, which perturbs one minterm by changing one gate’s functionality and then restores the perturbed circuit with a separated camouflaged block, achieving good resistance against the SAT-based attack. In this paper, we analyze the security vulnerabilities of CamoPerturb by illustrating the mechanism of minterm perturbation induced by gate replacement, then propose an attack to restore the changed gate’s functionality, and recover the camouflaged circuit. The attack algorithm is facilitated by sensitization and implication principles in automatic test pattern generation (ATPG) techniques. Experimental results demonstrate that our method is able to restore the camouflaged circuits with very little time consumption.

An Efficient SAT-Based Test Generation Algorithm with GPU Accelerator

This paper presents a novel framework comprises of a Propositional Satisfiability (SAT) encoder and solver. The framework responsible for generating and proving a simplified SAT-based formula of digital circuits for Automatic Test Pattern Generation (ATPG) proposes. The parallel algorithms introduced in this work are aimed at both combinational and sequential circuits and optimized on NVIDIA General-Purpose Graphics Processing Unit (GPGPU) paradigm. The SAT encoder presents an efficient method to apply the Boolean Constraint Propagation (BCP) on-the-fly while the generation is running on the GPU. The simplified formula is further proved for satisfiability using an improved parallel solver on GPU. The proposed encoder executes 93 times faster compared to the sequential counterpart. The test generation algorithm using the GPU-accelerated framework delivers about 5.86 speedup on an average compared to the state-of-the-art Lingeling solver. Moreover, the SAT encoder reduced the run time for fault detection by 6.53 and 11.42% on an average when applied to the proposed and the conventional CUD@SAT solvers, respectively, offering promising related work for the future research.