A Specification-Based Semi-Formal Functional Verification Method by a Stage Transition Graph Model

Abstract

The semi-formal verification method, in which the functionality is formally specified and the checking is undertaken through the formal model-based simulation, has been a promising choice for the functional verification of hardware designs. The existing methods derive the formal model from design implementation. This causes poor scalability and practicality. A more feasible solution is to derive the formal model directly from the specification. In this paper, we propose a specification-based semi-formal method for functional verification. The proposed semi-formal method uses a stage transition graph (STG) model to formally describe the function points in the specification. Meanwhile, we propose an automatic test pattern generation (ATPG) method to generate the test vectors based on the STG model. The proposed STG-based ATPG method can reach possible corner cases and ensure exhaustive exploration of functionality for both control-dominated designs and data-dominated designs. Moreover, we develop an STG-based tool for automatic verification. Our experiments show that our method can automatically verify the functional correctness from the specification while achieving similar code coverage as implementation-based semi-formal approaches.