Abstract
In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.
Highlights
Field-Programmable Gate Arrays (FPGAs) are 2-D arrays of Configurable Logic Blocks (CLBs) and programmable switch matrices, surrounded by programmable input/output blocks on the periphery
FPGAs are widely used in many applications such as networking, storage systems, communication, and adaptive computing, due to their reprogrammability, flexibility, and reduced time-to-market
The reprogrammability of FPGAs results in faster design and debug cycle compared to Application-Specific Integrated Circuits (ASICs)
Summary
Field-Programmable Gate Arrays (FPGAs) are 2-D arrays of Configurable Logic Blocks (CLBs) and programmable switch matrices, surrounded by programmable input/output blocks on the periphery. Application-dependent test and diagnosis are very crucial in online self-repair schemes for fault tolerant applications [2]. A novel BIST design with comprehensive on-the-fly exhaustive redundancy search and analysis method is presented in [13], which allows on-chip optimal redundancy allocation without having to construct the complete failed bitmap. It has high hardware overhead for a reasonably big number of spare (redundant) elements. The proposed method does not increase the test time for the fault-free memories It results in a much shorter diagnosis time than the conventional BISD schemes. An acceptable RA algorithm for BIST implementation should be considered for the repair efficiency and the hardware overhead of the BISR circuit
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