A BIST architecture for FPGA look up table testing reduces reconfigurations

Abstract

This paper describes a test architecture for minimum number of test configurations for test of FPGA (field programmable gate array) LUTs (look up tables). Our test architecture includes a TPG (test pattern generator) that is tested while it is generating test data for LE (logic elements) that form our CUT (circuit under test). This scheme eliminates the need for switching LEs between CUT, TPG and ORA (output response analyzer) and having to perform many reconfigurations of the FPGA. An external ORA locates faults of the FPGA under test. In addition to the LUTs, we are also presenting a scheme for testing other parts of the LEs. Compared with other methods, our method uses the least number of reconfigurations of an FPGA for its LUT testing.