A BIST scheme for testing the interconnects of SRAM-based FPGAs

Abstract

This paper discusses a new testing scheme for testing the interconnect resources in the Xilinx XC4000 series field programmable gate arrays (FPGAs). The scheme is based on the concept of built in self test (BIST), which subdivides the test problem into a test pattern generator (TPG), a circuit under test (CUT) and an output response analyzer (ORA). The research involves the location and detection of single-stuck-at and bridging and open faults that might be present in the interconnect network. The test responses obtained at the output of the ORA are stored in the look up table (LUT) of the configurable logic block (CLB) so that the faulty interconnect can be detected and located. This testing scheme ensures high reliability, increased fault tolerance capacity and provides maximal fault coverage. Reduced system time, zero circuit overhead and unity test resolution are some of the highlights of this new testing scheme.