Ternary Content Addressable Memory Architecture Research Articles

A novel algorithmic Data-Collision SDRAM-based TCAM architecture on FPGA

Ternary Content-Addressable Memory (TCAM) is one of the most effective methods for high-speed data searching in networking infrastructure. Despite the excellent performance and large look-up table, application-specific integrated- circuit-based TCAMs cost massive power supply and are challenging to configure. Field-Programmable Gate Arrays (FPGAs) have become the alternative solution for integrating TCAM due to their minimal power consumption and reconfigurability. Methods using on-chip registers, BRAMs, or LUTRAMs to implement large-size TCAM suffer excessive resource consumption. Researchers introduced DDR-SDRAM-based CAM to provide high-performance and economic packet inspections to overcome such issues; however, they only support binary look-up. This paper presents a novel algorithmic Data-Collision TCAM architecture on FPGA for SDRAM compatibility. The proposed SDRAM- based TCAM supports ternary value look-up function for practical Ethernet packet processing. The architecture outperforms conventional TCAMs regarding BRAMs, logics consumption, and look-up table sizes. The proposed architecture is the first SDRAM-based TCAM on FPGA with a 128Mbyte look-up table.

Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs

Field-programmable gate arrays (FPGAs) having software-like reconfigurability and hardware-like performance are adopted as developing platforms to implement complex systems, i.e., software-defined networks (SDNs). Ternary content-addressable memory (TCAM) is not present in modern FPGA, but rather it is used as a softcore where needed. The hardware structure of an FPGA is flexible but rigid; the elemental structure is fixed and can be used in a limited number of ways. Existing FPGA-based TCAMs exhaust one particular type of memory when a large size is implemented, resulting in a shortage of memory for the rest of the system. Our proposed architecture uses only those memory elements of FPGA that are redundant and not used by other parts. In this letter, the proposed architecture, comp-TCAM, combines both block RAM (BRAM) and lookup table RAM (LUTRAM) to implement the TCAM architecture; that eliminates the dependency on the type of memory and is adaptable to the requirement of the system. Evaluation results show the feasibility, scalability, and effectiveness of the proposed TCAM architecture compared to the existing TCAM architectures. The hardware resource utilization on Xilinx VIrtex-7 FPGA is reduced by 41.6% compared to state-of-the-art FPGA-based TCAM with no harm to the system’s performance providing a throughput of 21.06 Gbits/s.

A modular approach to design ternary content addressable memory architecture in quantum dot cellular automata

A modular approach to design ternary content addressable memory architecture in quantum dot cellular automata

RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs

Software-defined networks (SDNs) are the future networks that enable the system to be more flexible and programmable using a centralized controller. Field-programmable gate arrays (FPGAs) serve as exemplary hardware to implement these adaptable networks. Ternary content-addressable memory (TCAM) is an essential part of every network to perform packet classification and forwarding, but they are missing in modern FPGAs. Researchers and FPGA vendors have proposed several designs to emulate TCAM using available memories on FPGA, but they are power inefficient due to the activating of entire circuitry in a single search operation. In this brief, we propose a novel power-aware reconfigurable FPGA-based TCAM architecture that enables only a portion of the hardware to perform the search operation. We performed an extensive design space exploration to find the optimal number of banks on Xilinx FPGAs, which provides the maximum power saving. Moreover, we propose a solution to bank overflow using backup CAM (BUC) to handle the overflowed CAM entries. The proposed TCAM improves the power consumption by 40% and maintains one-clock cycle update latency with no compromise on the throughput of the system compared with the state-of-the-art FPGA-based TCAM architectures.

Multi-Core Eight Bit Ternary Content-Addressable Memory Design Based Image Learning System

In this research work, the image is learned to find features to make use of during its analysis and a genetic apices based low power Ternary Content-Addressable Memory (TCAM) is designed to implement the proposed image learning system. A technique called Content Matching Search Register is proposed in this work to perform the image learning operations in proposed TCAM architecture. This paper proposes an ImOFF algorithm for image analysis. The focus of this multi-core TCAM (MC-TCAM) is to make fast computations and search based designs. The focus application of this research work is in the design of low power On-board Embedded-VLSI chip to perform image analysis. Proposed multi-core eight bit Ternary TCAM (MCEB-TCAM) is analyzed using IC design tools in 90nm technology, using Verilog hardware description language and usage of Cadence for layout generation and parasitic extraction of the circuit components.

Ternary content addressable memory for longest prefix matching based on random access memory on field programmable gate array

Conventional ternary content addressable memory (TCAM) provides access to stored data, which consists of '0', '1' and ‘don't care’, and outputs the matched address. Content lookup in TCAM can be done in a single cycle, which makes it very important in applications such as address lookup and deep-packet inspection. This paper proposes an improved TCAM architecture with fast update functionality. To support longest prefix matching (LPM), LPM logic are needed to the proposed TCAM. The latency of the proposed LPM logic is dependent on the number of matching addresses in address prefix comparison. In order to improve the throughput, parallel LPM logic is added to improve the throughput by 10× compared to the one without. Although with resource overhead, the cost of throughput per bit is less as compared to the one without parallel LPM logic.

Low Power High Speed Ternary Content Addressable Memory

Compared to Binary Content Addressable Memory (BiCAM) there are many applications for Ternary Content Addressable Memory (TCAM) as a search engine. But TCAM consumes more power than BiCAM. So, the saving of TCAM power consumption is the main objective of numerous designs. Precharge phase of the TCAM leads to more power consumption. Newly, a precharge free NOR type BiCAM has been suggested but it takes more time for its operation. Here, precharge free high speed NOR type TCAM is proposed. The proposed TCAM architecture takes power same as precharge free NOR type TCAM but its delay has been reduced by 84% . Simulations performed with cadence 45-nm technology at the supply voltage of 1V.

D-TCAM: A High-Performance Distributed RAM Based TCAM Architecture on FPGAs

Ternary content-addressable memory (TCAM) is a high-speed searching device that searches the entire memory in parallel in deterministic time, unlike random-access memory (RAM), which searches sequentially. A network router classifies and forwards a data packet with the aid of a TCAM that stores the routing data in a table. Field-programmable gate arrays (FPGAs), due to its hardware-like performance and software-like reconfigurability, are widely used in networking systems where TCAM is an essential component. TCAM is not included in modern FPGAs, which leads to the emulation of TCAM using available resources on FPGA. Several emulated TCAM designs are presented but they lack the efficient utilization of FPGA's hardware resources. In this paper, we present a novel TCAM architecture, the distributed RAM based TCAM (D-TCAM), using D-CAM as a building block. One D-CAM block implements a 48-bytes TCAM using 64 lookup tables (LUTs), that is cascaded horizontally and vertically to increase the width and depth of TCAM, respectively. A sample size of 512 x 144 is implemented on Xilinx Virtex-6 FPGA, which reduced the hardware utilization by 60% compared to the state-of-the-art FPGA-based TCAMs. Similarly, by exploiting the LUT-flip-flip (LUT-FF) pair nature of Xilinx FPGAs, the proposed TCAM architecture improves throughput by 58.8% without any additional hardware cost.

Approximate Computing Using Multiple-Access Single-Charge Associative Memory

Memory-based computing using associative memory is a promising way to reduce the energy consumption of important classes of streaming applications by avoiding redundant computations. A set of frequent patterns that represent basic functions are pre-stored in Ternary Content Addressable Memory (TCAM) and reused. The primary limitation to using associative memory in modern parallel processors is the large search energy required by TCAMs. In TCAMs, all rows that match, except hit rows, precharge and discharge for every search operation, resulting in high energy consumption. In this paper, we propose a new Multiple-Access Single-Charge (MASC) TCAM architecture which is capable of searching TCAM contents multiple times with only a single precharge cycle. In contrast to previous designs, the MASC TCAM keeps the match-line voltage of all miss-rows high and uses their charge for the next search operation, while only the hit rows discharge. We use periodic refresh to control the accuracy of the search. We also implement a new type of approximate associative memory by setting longer refresh times for MASC TCAMs, which yields search results within 1–2 bit Hamming distances of the exact value. To further decrease the energy consumption of MASC TCAM and reduce the area, we implement MASC with crossbar TCAMs. Our evaluation on AMD Southern Island GPU shows that using MASC (crossbar MASC) associative memory can improve the average floating point units energy efficiency by 33.4, 38.1, and 36.7 percent (37.7, 42.6, and 43.1 percent) for exact matching, selective 1-HD and 2-HD approximations respectively, providing an acceptable quality of service (PSNR > 30 dB and average relative error <10 percent). This shows that MASC (crossbar MASC) can achieve 1.77X (1.93X) higher energy savings as compared to the state of the art implementation of GPGPU that uses voltage overscaling on TCAM.

Unified nvTCAM and sTCAM architecture for improving packet matching performance

Software-Defined Networking (SDN) allows controlling applications to install fine-grained forwarding policies in the underlying switches. Ternary Content Addressable Memory (TCAM) enables fast lookups in hardware switches with flexible wildcard rule patterns. However, the performance of packet processing is severely constrained by the capacity of TCAM, which aggravates the processing burden and latency issues. In this paper, we propose a hybrid TCAM architecture which consists of NVM-based TCAM (nvTCAM) and SRAM-based TCAM (sTCAM), utilizing nvTCAM to cache the most popular rules to improve cache-hit-ratio while relying on a very small-size sTCAM to handle cache-miss traffic to effectively decrease update latency. Considering the special rule dependency, we present an efficient Rule Migration Replacement (RMR) policy to make full utilization of both nvTCAM and sTCAM to obtain better performance. Experimental results show that the proposed architecture outperforms current TCAM architectures.

TCAM-Based Multi-Match Packet Classification Using Multidimensional Rule Layering

Ternary content addressable memory (TCAM) has superior performance for single-match packet classification but not the case for multi-match packet classification. The limitation is caused by TCAM architecture that reports only the first matching rule. To cope with the limitation, previous algorithms use extra TCAM entries or accesses, or both, to fulfill multi-match packet classification. These algorithms also reorder rules; thus, a multi-match classifier based on these algorithms cannot maintain performance for single-match packet classification. In other words, all matching rules must be yielded to determine the highest priority matching rule. In this paper, we present a TCAM-based scheme for multi-match packet classification without single-match penalty. Our scheme partitions a rule set based on range layering, which can be applied to achieve range encoding. The rule partitioning generates rule subsets which satisfy that the rules in a subset are mutually disjoint. Each rule is then tagged a bitmap for subset identification to fulfill multi-match packet classification. Two approaches, loose coupling and tight coupling, are derived with different search procedures while incorporating range encoding. Both approaches can maintain original rule order, but with different performance tradeoff. We also present a refinement which uses all available TCAM entries to improve the performance of multi-match packet classification. The experimental results show that combining range encoding with multi-match packet classification has advantages of storage efficiency and speed superiority. The capability of supporting single-match packet classification also provides better flexibility of applying different packet actions.

A Memory-Efficient TCAM Coprocessor for IPv4/IPv6 Routing Table Update

Ternary content-addressable memory (TCAM) is a simple hardware device for fast IP lookups that can perform a lookup per cycle. However, prefixes may be inserted into or deleted from the TCAM because of changes in Internet topology. Traditional TCAM coprocessors maintain the enclosure relationship among prefixes by using an extended binary trie and perform TCAM movements based on an update algorithm (e.g., CAO_OPT) which runs on a local CPU to maintain the speed and correctness of the TCAM search process. In this paper, we propose a memory-efficient TCAM coprocessor architecture for updates that require only small memory size compared with the extended binary trie. The average number of TCAM movements per update is almost the same as that of CAO_OPT. However, the time to compute how to move TCAM entries in the proposed TCAM coprocessor is less than that in CAO_OPT. Only a small part of total TCAM search cycles is used to complete our update process. The proposed TCAM architecture can also be made smaller and faster because large off-chip memory for the extended binary trie and a local CPU are no longer necessary.

Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating

Ternary content-addressable memory (TCAM) is a popular hardware device for fast routing lookup and an attractive solution for applications such as packet forwarding and classification. However, the high cost and power consumption are limiting its popularity and versatility. In this paper, a low leakage power TCAM architecture which uses two-side self power gating technique is proposed to reduce the leakage power dissipation of the mask SRAM cells. The TCAM mask cells are divided into several segments, and the mask bits of one segment are the same except for the boundary segment. In this design, the boundary segment is activated and the others are disabled so that the leakage power can be reduced. The experimental results show that average 26% leakage power can be reduced by using UMC 90 nm CMOS process with 1.0 V supply voltage when compared with the traditional TCAM architecture.

A 65 nm 0.165 fJ/Bit/Search 256$\,\times\,$144 TCAM Macro Design for IPv6 Lookup Tables

Ternary content addressable memory (TCAM) is extensively adopted in network systems. As routing tables become larger, energy consumption and leakage current become increasingly important issues in the design of TCAM in nano-scale technologies. This work presents a novel 65 nm energy-efficient TCAM macro design for IPv6 applications. The proposed TCAM employs the concept of architecture and circuit co-design. To achieve an energy-efficient TCAM architecture, a butterfly match-line scheme and a hierarchy search-line scheme are developed to reduce significantly both the search time and power consumption. The match-lines are also implemented using noise-tolerant XOR-based conditional keepers to reduce not only the search time but also the power consumption. To reduce the increasing leakage power in advanced technologies, the proposed TCAM design utilizes two power gating techniques, namely super cut-off power gating and multi-mode data-retention power gating. An energy-efficient 256 × 144 TCAM macro is implemented using UMC 65 nm CMOS technology, and the experimental results demonstrate a leakage power reduction of 19.3% and an energy metric of the TCAM macro of 0.165 fJ/bit/search.

A New TCAM Architecture for Managing ACL in Routers

SUMMARY Ternary Content Addressable Memory (TCAM) is a special type of memory used in routers to achieve high-speed packet forwarding and classification. Packet forwarding is done by referring to the rules written in the routing table, whereas packet classification is performed by referring to the rules in the Access Control List (ACL). TCAM uses more transistors than Random Access Memory (RAM), resulting in high power consumption and high production cost. Therefore, it is necessary to reduce the entries written in the TCAM to reduce the transistor count. In this paper, we propose a new TCAM architecture by using Range Matching Devices (RMD) integrated within the TCAM’s control logic with an optimized prefix expansion algorithm. The proposed method reduces the number of entries required to express ACL rules, especially when specifying port ranges. With less than 10 RMDs, the total number of lines required to write port ranges in the TCAM can be reduced to approximately 50%.

A 2-Level TCAM Architecture for Ranges

As the demand for high-quality Internet increases, emerging network applications are spurring the need for faster, feature-rich, and cost-effective routers. Multifield packet classification in routers has been a computation-intensive data path function for software implementation. Therefore, solutions for packet classification based on hardware design, such as Ternary Content Addressable Memory (TCAM), are necessary to sustain gigabit line processing rate. Traditionally, TCAMs have been designed for storing prefixes. However, multifield packet classification usually involves two fields of arbitrary ranges that are TCP/IP layer 4 source and destination ports. Storing ranges in TCAMs relies on decomposing each individual range into multiple prefixes, which leads to range-to-prefix blowout. To reduce the total number of prefixes needed to represent all ranges, this paper proposes a 2-level TCAM architecture and two range-to-prefix conversion schemes. In the first proposed scheme, designed for disjoint ranges, the maximum number of entries needed in TCAM is 2m-1 for m disjoint ranges. In the second proposed scheme, designed for contiguous ranges, only m TCAM entries are needed. In a general case of n arbitrary ranges, all ranges can first be converted into disjoint ranges or contiguous ranges and then the proposed algorithms can be applied. As a result, only 4n-3 TCAM entries are needed for the disjoint ranges and only 2n+1 TCAM entries are needed for contiguous ranges. This paper also proposes insertion and deletion algorithms to accommodate incremental changes to the range sets. The experiments made show that the proposed range-to-prefix conversion schemes perform better than the existing schemes in terms of the number of required TCAM entries and execution time for range update operations.