Temperature Instability Degradation Research Articles

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

DC to AC analysis of HC vs. BTI damage in N-EDMOS used in single photon avalanche diode cell

N-channel Extended Drain Metal Oxide Semiconductor (EDMOS) device is analysed through its sensitivity to Hot-Carrier (HC), hot hole (HH) injections and Positive Bias Temperature (PBT) instability degradation using accelerated DC to AC lifetime technique. EDMOS device is optimized for an effective gate-length Leff = 0.25 μm, with a gate-oxide thickness Tox = 5 nm operating at a frequency of 3 MHz at nominal supply voltage VDD = 5 V. The device is used in a mixed structure dedicated to 3D integration of Single Photon Avalanche Diode (SPAD). We show that HC reliability of EDMOS transistor can be obtained using worst-case DC accelerating degradation at high temperature transferred to the real AC waveforms applied to N-channel device placed into the SPAD cell. This allows to deduce the AC device lifetime obtained from DC stressing using a quasi-static approach considering the dominant degradation mechanism at condition of maximum gate-voltage VGSmax. This is explained by the optimized structure in Tox, VDD and lateral isolation where PBT, Off mode and recovery effects have limited impacts during switching operation of the N-EDMOS device used in SPAD circuit environment.

Run-Time Thermal Management for Lifetime Optimization in Low-Power Designs

In this paper, the magnitude of the temperature and stress variability of dynamic voltage and frequency scaling (DVFS) designs is analyzed, and their impact on the bias temperature instability (BTI) degradation and lifetime of DVFS designs is assessed. For this purpose, a design-time evaluation framework for BTI degradation was developed, which considered the statistical workload and die temperature profiles of DVFS operating modes. The performed analysis showed that, together with high stress variability, DVFS designs exhibited even higher temperature variability, depending on the workload and utilized operating modes, and the impact of temperature variability on lifetime could be up to 2× higher than that due to stress. In order to account for temperature variability on aging detrimental effects, a thermal management run-time system is proposed that honors the desired lifetime constraints by properly selecting temperature constraints that govern the utilized operating modes. The proposed run-time system was applied on the largest benchmark circuit from the IWLS 2005 suite, Ethernet circuit, synthesized with the 32 nm CMOS technology. The proposed system was verified to obtain lifetime and performance estimation and the trade-off with up to 35.8% and 26.3% higher accuracy, respectively, when compared to a system that ignores temperature variability and accounts for average temperature only. The proposed framework can be suitably utilized for tuning run-time throttling policies of low-power designs, thus allowing designers to optimize lifetime–performance trade-offs, depending on the requirements mandated by specific applications and operating environments.

Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

Design and Simulation for NBTI Aware Logic Gates

Reliability of the electronic circuits is one of the most prominent factor in the development of very large-scale integration (VLSI) industry. Huge demand for compact size and high performance of electronic devices leads the excessive scaling of the transistor. Aggressive scaling of transistor in ultra-deep submicron regime arises the problem of short channel effects (SCEs) which is the major reason for subthreshold leakage and reliability issues. Negative input voltage to p-channel metal oxide semiconductor (PMOS) transistor causes interface traps at silicon dioxide and silicon substrate interface which leads to increase in the threshold voltage of the transistor and degrades the circuit performance. The design parameters exceed the design specification and causes the variations in timing due to negative bias temperature instability (NBTI) degradation that results logic failure. This paper presents the impact of reliability variations on 32 nm complementary metal oxide semiconductor (CMOS) predictive technology model (PTM) and 20 nm multi-gate PTM fin-shaped field effect transistor (FinFET) circuits. NBTI degradation of various circuits are evaluated with the help of Cadence’s virtuoso tool containing Spectre native reliability simulator. Simulation results are showing that NBTI degradation causes variations in threshold voltage and alters the output performance.

A statistical study into reliability of FPGA implemented circuits: Simulation and modelling

In this work, we report on the development of a methodology to study the reliability of digital circuits implemented in FPGA. For this, the design and simulation tools have been extended to introduce aging. The aging laws for Look-Up Tables, describing the drifts in the propagation time, caused by Hot Carrier Injection and Negative Bias Temperature Instability degradation mechanisms, have been integrated into the simulation environment by introducing additional variables and equations. Moreover, the study has been further extended by considering the statistical dispersion in the failure time due to different sources of dispersion. Furthermore, an analytical and a statistical model of the failure time of the digital circuit as a function of the clock frequency, aging law parameters and dispersion parameters have been proposed. Finally, the developed methodology has been applied to two different digital circuits implemented in FPGA.

Mixed Hot-Carrier/Bias Temperature Instability Degradation Regimes in Full {V G, V D} Bias Space: Implications and Peculiarities

Characterizing mixed hot-carrier/bias temperature instability (BTI) degradation in full { $\textit {V}_{\text{G}}$ , $\textit {V}_{\text{D}}$ } bias space is a challenging task. Therefore, studies usually focus on individual degradation mechanisms, such as BTI and hot-carrier degradation (HCD). However, a simple superposition of these mechanisms at an arbitrary { $\textit {V}_{\text{G}}$ , $\textit {V}_{\text{D}}$ } combination often fails to predict the cumulative damage. We experimentally acquired a large data set covering the full bias space of a pMOSFET which allows us to obtain detailed degradation and recovery maps. Our models for describing oxide and interface defects provide physical insights into the underlying mechanisms and a possible interplay between the degradation modes. Additionally, we perform a dedicated experiment to reveal the implications of different stress regimes onto the various types of defects by switching BTI and HCD stress conditions. The results clearly reveal the conceptual limits of the assumption of independent degradation regimes.

Characterization of fast relaxation by oxide-trapped charges under BTI stress on 64 nm HfSiON/SiO2 MOSFETs

For HfSiON/SiO2 n-type and p-type MOSFETs with a channel length L = 64 nm, the fast relaxation effect of oxide-trapped charges Qox during interrupt for bias temperature instability (BTI) degradation measurement were investigated, and a model that compensated for this effect to predict lifetime tL was proposed. Experimental results show that the fast relaxation of Qox during threshold-voltage Vth measurement rapidly saturates within 1 s and is exponentially increasing for gate stress voltage Vg,str and exponentially decreasing for measurement duration tm but does not affect the BTI degradation mechanism. Using the Vg,str and tm dependence of Qox’s fast relaxation under BTI stress, tL prediction model was proposed to compensate the recovery effect by Vth measurement from BTI degradation measured in slow measurement (SM) condition with tm > 1 μs. The proposed model increases the precision of the estimate of tL by considering the recovery effect of Qox even in SM.

Impacts of NBTI and hot-carrier stress on silicon nanowire transistor characteristics

Following the downscaling road map for planar metal–oxide–semiconductor field-effect transistors, non-planar (three-dimensional) multiple-gate architectures are becoming essential for the ultimate scaling of complementary metal–oxide–semiconductor devices. Gate-all-around (nanowire) field-effect transistors have proven to be the most suitable below-22 nm technology nodes. Hence the reliability of these devices is of great concern. Negative-bias temperature instability (NBTI) and hot-carrier degradation (HCD) are the key device reliability issues that exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) under direct-current and alternating-current stress were investigated. When stressed, the NBTI behavior in SNWTs showed fast initial degradation, quick degradation saturation and then a special recovery behavior. Along with that, the effects of hot-carrier stress on n-channel SNWTs were studied. Due to the surrounded gate structure, it was observed that the effects of HCD were significant in the nanowire transistors.

Channel-length dependence of mechanical stress effect by hybrid shallow trench isolation on NBTI degradation of HfSiON/SiO2p-channel MOSFETs with strained Si/SiGe channel

This paper quantifies how mechanical stress induced by the hybrid shallow trench isolation affects negative bias temperature instability (NBTI) degradation of p-type channel MOSFETs (pMOSFETs) that have a strained Si/SiGe channel. As the channel length L decreased, the NBTI degradation decreased and electrical characteristics degraded. Experimental results indicate that tensile stress σt applied to the channel region decreased the energy band-gap by increasing the intrinsic carrier concentration. NBTI degradation was not affected by application of an oxide electric field to compensate for the charge that is induced differently in the Si channel during strong inversion. The distribution of the shift ΔVth of threshold voltage before and after NBTI stress in the channel region was also examined. As L decreased, the decrease of ΔVth was greater in the gate edge region than in the center region. These results show that the observed L-dependence of NBTI degradation characteristics were caused by σt in the channel region, and affected the gate edge region dominantly. Therefore, to achieve reliable high-k pMOSFETs with the strained Si/SiGe channel as L is scaled down, methods should be developed to control mechanical stress in the gate edge region.

New Insight Into Negative Bias Temperature Instability Degradation During Self-Heating in Nanoscale Bulk FinFETs

In this letter, we investigate the threshold voltage shift ( $\Delta {V} _{\textsf {th}}$ ) by negative bias temperature instability (NBTI) coupled with the self-heating effect (SHE) in a 14-nm bulk ${p}$ -FinFET. To analyze the effect of NBTI in the presence of the SHE, the DC stress was performed under high-bias conditions, i.e., gate bias ${V}_{\textsf {GS}} = -{1.3}$ V and drain bias ${V}_{\textsf {DS}}$ up to −1.3 V at room temperature, which was usually referred to as hot-carrier degradation (HCD) stress. It has been observed that the long-time (10 s ~ 103 s) power-law time exponent ( ${n}$ ) decreases as ${V}_{\textsf {DS}}$ increases, and ${n}$ was very close to that of NBTI-induced $\Delta {V} _{\textsf {th}}$ rather than HCD-induced $\Delta {V} _{\textsf {th}}$ at ${V}_{\textsf {GS}} = {V}_{\textsf {DS}} = -{1.3}$ V. For the first time, computer-aided design simulations were performed in combination with SHE and NBTI. The effect of NBTI in ${p}$ -FinFET is confirmed to contribute significantly to $\Delta {V} _{\textsf {th}}$ under DC HCD stress because of SHE. The influence of SHE is mitigated in high-frequency circuit operation, but special attention should be paid to NBTI issues due to the potential occurrence of SHE as the technology nodes shrink.

An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI

Bias temperature instability (BTI) degradation poses increasingly critical lifetime reliability design challenges in static random access memory (SRAM), as fabrication technology marches toward a very deep nanometer regime. This paper presents circuit techniques that enable on-chip dynamic reliability management, which intelligently monitors and mitigates the half-selected cell stability failure due to BTI degradation in SRAM. The dynamic reliability management is achieved through the automated BTI-aware write word-line (WWL) control, whereby it detects the BTI degradation in SRAM cells through a replica row-based BTI-aware stability monitor and adjusts the WWL voltage level with two-phase write operation (TPWO). The WWL voltage level is divided into two phases to maintain the half-selected cell stability with BTI without compromising other circuit parameters. Silicon validation of a 16-kb SRAM based on a 28-nm fully depleted silicon on insulator (FDSOI) technology successfully demonstrates that the half-selected cell stability failure is eliminated from 57.13% down to 0% with the proposed approach at a marginal 3.42% power and 10% area overheads.

NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling

We investigate the negative-bias temperature instability (NBTI) degradation and recovery of pMOSFETs under continuously varying analog-circuit stress voltages and thereby generalize existing digital-stress NBTI studies. Starting from our ultrafast NBTI measurements and an extensive TCAD analysis, we study two physics-based compact models for analog-stress NBTI including recovery. The high accuracy of both models is evidenced from single-FET analog-stress and circuit-level ring oscillator experiments. Their numerical efficiency allows direct coupling to circuit simulators and permits to accurately account for NBTI already during circuit design. Furthermore, one of the models calculates the time-dependent NBTI variability of single-FET and of circuit performance parameters. We demonstrate our NBTI models on a ring oscillator and calculate the mean drift and statistical distribution of its oscillation frequency.

The role of the disordered HfO2 network in the high-κ n-MOSFET shallow electron trapping

Current understanding of the bias temperature instability degradation usually comprises two parts: (1) shallow-level component that can recover within a short time and (2) deep level traps that the emission time of the trapped carrier is extremely long. Prevenient studies of the positive bias temperature instability degradation in the high-κ n-MOSFET indicate that oxygen vacancy (VO) is the dominant defect type that responds for the shallow electron trapping. However, recent experimental results reveal that the VO defect density required to accommodate the experimental measured recoverable threshold voltage degradation (ΔVth) is much higher than that of the reasonable atomic structure in the amorphous HfO2. On the other hand, investigations on the disordered Hf-O-Hf network in the amorphous HfO2 reveal their capabilities as charge trapping centers; therefore, in this work, atomic simulation work is performed, and our results show that the disordered Hf-O-Hf networks can act as effective electron capture centers with shallow levels near the Si conduction band. Moreover, the high density of the stretched Hf-O-Hf networks in the amorphous HfO2 also significantly enriches the shallow electron traps in the oxide.

Investigation of PBTI Degradation in Nanosheet nFETs With HfO2 Gate Dielectric by 3D-KMC Method

Stacked nanosheet transistor (NST) has been regarded as a promising candidate to enable scaling beyond FinFET for the sub-5 nm technology node due to the superior performance. However, reliability optimization from the physical perspective, which is essential for the guideline of NST cell design, still remains unclear. In this paper, we investigate positive bias temperature instability (PBTI) degradation in the ultra-scaled n-type NST with HfO2 gate dielectric by three-dimensional-kinetic Monte Carlo method considering multiple microscopic mechanisms. Gate voltage bias and temperature dependent PBTI characteristics are presented. Furthermore, the impacts of width (Wsh) and height (Hsh), key design parameters for NST, on PBTI degradation and threshold voltage shift (ΔVth) variation are evaluated. The results show that with the larger Wsh/Hsh, PBTI becomes severer but suffers less variation and the high temperature enlarges ΔVth variation. In the case of same device perimeter, PBTI is more sensitive to the narrow Hsh side.

SUBHDIP: process variations tolerant subthreshold Darlington pair‐based NBTI sensor circuit

Aggressive technology scaling has inevitably led to reliability becomes a major concern for modern high-speed and high-performance integrated circuits. The major reliability concerns in nanoscale very-large-scale integration design are the time-dependent negative bias temperature instability (NBTI) degradation. Owing to increasing vertical oxide field and higher operating temperature, the threshold voltage of P-channel MOS transistors increases with time under NBTI. This study presents a novel subthreshold Darlington pair-based NBTI degradation sensor under the stress conditions. The proposed sensor provides the high degree of linearity and sensitivity under subthreshold conditions. The Darlington pair used in the circuit provides the stability and the high-input impedance of the circuit makes it less affected by the process variations. Owing to high sensitivity, the proposed sensor is best suited for sensing of temperature variation, process variation, and temporal degradation during measurement. The sensitivity of the proposed sensor at room temperature is 0.239 mV/nA under subthreshold conditions. The proposed sensor is less affected by the process variation and has the maximum deviation of 0.0011 mV at standby leakage current of 30 nA.

Simulation and modelling of long term reliability of digital circuits implemented in FPGA

In this work, we report on the development of a methodology for long term reliability analysis of digital circuits implemented in FPGA. For this, a simulation environment for FPGA has been extended using Python to introduce aging. The aging laws for Look-Up Tables have been integrated by introducing additional variables and equations. They accurately describe the drifts in the propagation time caused by Hot Carrier Injection and Negative Bias Temperature Instability degradation mechanisms. An analytical model of the failure time of the digital circuit as a function of the clock frequency has been proposed based on the aging law parameters. Finally, the developed methodology has been applied to a CORDIC circuit implemented in FPGA.

Impact of NBTI Stress on VDMOSFET Regions

In this paper, we investigate the impact of negative bias temperature instability (NBTI) degradation on both channel and drain regions, of commercial power double diffused MOS transistor (VDMOSFET), using capacitance-voltage method (C-V). We report that the degradation is important at channel (drain) region in p-channel VDMOSFET (n-channel VDMOSFET). That means that the phosphorus doped region (n-type) is more sensitive to NBTI stress.

An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells

Aggressive technology scaling causes unavoidable reliability issues in modern high-performance integrated circuits. The major reliability factors in nanoscale VLSI design is the negative bias temperature instability (NBTI) degradation and soft-errors in the space and terrestrial environment. In this paper, an on-chip analog adaptive body bias (OA-ABB) circuit to compensate the degradation due to NBTI aging is presented. The OA-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The OA-ABB consists of standby leakage current sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of 10 years NBTI aging. The proposed OA-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of OA-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.61%, 1.48%, and 0.72% respectively by using OA-ABB to compensate the degradation. The figure of merit of 6T SRAM cell also improved by 17.24% with the use of OA-ABB.