Abstract
The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.
Highlights
Field-programmable gate arrays (FPGAs) are eminently utilized to develop the latest complementary metal oxide semiconductor (CMOS) technology due to their high volume density, scalability, and ability to cope with the highest performance demands for digital and mixed-mode analog applications
Numerous reports elaborate on delays that occur in FPGAs, which are detrimental to chip performance [5,6,7,8,9,10]
It has been reported that the delay is the effect of a negative bias temperature instability (NBTI), which is a critical factor of FPGA degradation [17,18,19]
Summary
Field-programmable gate arrays (FPGAs) are eminently utilized to develop the latest complementary metal oxide semiconductor (CMOS) technology due to their high volume density, scalability, and ability to cope with the highest performance demands for digital and mixed-mode analog applications. After the rapid downscaling in FPGAs, the device encounters challenges, including increased noise sensitivity, manufacturing variability, and reliability concerns [1,2,3,4]. These factors escalate the degradation of the chip performance, which eventually reduces the lifespan of the product. It has been reported that the delay is the effect of a negative bias temperature instability (NBTI), which is a critical factor of FPGA degradation [17,18,19]. Seven output ranges of a phase-detection aging sensor with a lifetime prediction table for different FPGAs manufacturers are proposed to guide system designers and industrial players through simulation and experimental validation.
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