Temperature Dependent Capacitance-voltage Research Articles

Understanding the trap-induced frequency dispersion in the C–V curve of AlGaN/GaN hetero-structure

This article investigates the trapping mechanism in AlGaN/GaN heterostructure. For our study, the traps within the AlGaN layer are introduced at the interface and near the interface of AlGaN/GaN, in the SILVACO TCAD tool. Frequency-dependent capacitance-Voltage (CVF) curves are obtained to study the impact of traps on device performance. From the CVF curve, it is found that the existence of interface traps introduces a shift in capacitance along the gate voltage axis. These traps introduce the threshold voltage ( VTH ) shift. Furthermore, a detailed study of near-interface traps (NITs) is done based on tunneling mechanisms. For our investigation, the NITs are positioned at 0.5 nm, 1 nm, and 1.5 nm away from the AlGaN/GaN interface. The response of the NITs reduces the capacitance value in the accumulation region. The response of the NITs is explained through the capacitance charge model and border trap model. For NITs placed 0.5 nm away from the interface, the frequency dispersion in the accumulation region becomes evident. On the contrary, the dispersion reduces significantly, as the NITs goes deeper upto 1.5 nm. The results indicate that the NITs nearer to the interface respond to high frequencies. Further, the temperature dependent capacitance–voltage analysis is done for both interface and NITs, to understand the effect of temperature on frequency dispersion.

Temperature dependence of capacitance–voltage characteristics of germanium telluride thin films

Temperature-dependent capacitance–voltage and conductance–voltage measurements of 200-nm-thick germanium telluride (GeTe) thin films deposited via direct current magnetron sputtering were investigated. Measurements were performed across a temperature range of 27–357 °C, with a sweep of voltage values from −20 to +20 V at an operating frequency of 1 MHz. An amorphous–crystalline transition temperature (Tc) of 197 °C was found. Below Tc, the GeTe films were highly resistive, and their capacitance was insensitive to the applied bias voltage and temperature. Above Tc, the capacitance showed strong dependence on temperature, owing to the triggering of GeTe crystallization incorporating nucleation and growth processes. Applied bias voltage did not show a profound impact on the GeTe capacitance even after crystallization, but it had an observable impact on the film conductance beyond 250 °C. Moreover, the GeTe thin film capacitance increased by a factor of 13 upon crystallization. Hall-effect measurements revealed that the film conductivity increased upon crystallization, as did the hole concentration and mobility. Cross-sectional transmission electron microscopy demonstrated that the GeTe thin films crystallize via a nucleation-dominated crystallization mechanism.

Synthesis of nickel nanoparticles-deposited strontium titanate nanocubes (Ni-STO) and heterojunction electrical applications over a wide temperature range

In the present study, the structural properties of nickel nanoparticles-deposited strontium titanate nanocubes (Ni-STO) were examined by taking XRD, ICP-MS, TEM and SEM images. Temperature-dependent capacitance–voltage (C-V) and current–voltage (I-V) measurements were made for the electrical characterization of the Ni/Ni-STO/n-Si heterojunction devices produced. As the temperature increases from 80 K to 400 K, the ideality factor (n) decreases from 2.30 to 1.02 while barrier height (BH) increases from 0.27 eV to 0.80 eV. In the heterojunction device between Ni-STO and n-type Si, electrons can be captured at the Schottky barrier interface and recombinations can be reduced. Devices produced with Ni-STO material had a positive effect on performance compared to the devices produced with STO in previous studies. The electrical parameters obtained give compatible results as a function of temperature. Metal deposited STOs are potential candidates for temperature-dependent sensors and electrical devices.

Deep Trap Characterization and the Kink Effect in AlGaN/GaN HEMTs

This article presents the study of trapping effects in AlGaN/GaN high electron mobility transistors (HEMTs). Conventional methods like temperature-dependent capacitance-voltage (CV) and pulsed-IV (PIV) have been employed to quantify the traps present in the device layers. Apparent threshold voltage (VTH) instability as well as lag in the drain current after pulsing are evident. The kink in the drain current has been taken up to observe the trapping signature for devices with two different gate lengths. A modified drain and gate pumping methodology which has been designated as pre-measurement run (PMR) has been presented to get a deeper insight into the kink effect in these devices. Constant maximum field (CMF) PMR shows substantial change in the drain current, whereas negligible change for variable maximum field (VMF) PMR is observed, which confirms the dominant impact of trapping within the heterostructure and field assisted detrapping through Poole-Frenkel emission. Multiple traps have also been identified within the epitaxial layers with the E2 trap (Ea (activation energy) = 0.69 eV) which can be held responsible for the kink observed in the DC characteristics as observed from pulsed drain lag characteristics.

A useful model to interpret the experimental I-V-T and C-V-T data of spatially inhomogeneous metal-semiconductor rectifying contacts

ABSTRACT The temperature-dependent capacitance-voltage (C-V) and current-voltage (I–V) characteristics of the Ti/p-InP/ZnAu Schottky contacts were investigated in this study. The current across a metal-semiconductor Schottky contact can vary sensitively with the change of the Schottky barrier heights (SBHs) and sample temperature. Thereby, the value of the C-V barrier height increased and the value of the I–V barrier height decreased with a decrease in temperature. Such a change was ascribed to a Gaussian distribution of the spatial inhomogeneity of the SBHs over whole range of the measurement temperatures. Thus, the temperature dependences of the I–V and C-V characteristics were interpreted by a quantitative analysis of spatial distribution (Gaussian distribution) of the SBHs presented as a useful model. Thus, this quantitative analysis was determined from the change of values with (2kT −1).

On the studies of capacitance–voltage and impedance spectroscopy of an Ni/(GO-Fe3O4)/n-Si heterojunction device over a wide temperature range

The purpose of this work is to fabricate a Ni/GO-Fe3O4/n-Si heterojunction device using Mott-Schottky plots and to study the capacitance–voltage/conductance/series resistance characteristics of the device as a function of temperature. We analyzed temperature dependent capacitance–voltage measurements for the Ni/GO-Fe3O4/n-Si device in the temperature range from 80 to 360 K. Temperature dependent electrical measurements have been performed at a fixed frequency of 500 kHz and frequency dependent ones have been carried out at room temperature. In the reverse bias capacitance–voltage characteristics figure, it has been determined that the barrier height is 1.73 eV (80 K) and 1.50 eV (360 K) with 20 K steps. The impedance analysis measurements have been performed in the reverse and forward biases. The experimental results have shown that the values of capacitance, conductance, interface states and series resistance Rs depend on both bias voltage and temperature.

Dielectric relaxation and magnetodielectric response of mesoporous terbium manganate nanopaticles

We report here the investigation on dielectric response, charge transport mechanism and magnetocapacitance of mesoporous perovskite Terbium Manganate (TMO) nanoparticles. TMO NPs possess relatively high specific surface area (20.9 m2 g−1) than that of general perovskite-type metal oxides. To study the dielectric/magnetodielectric response in TMO material, a capacitive system is fabricated. Impedence spectroscopy shows electrically heterogeneous nature of the material. Due to the existence of inhomogeneity at electrode-TMO interface, ideality factor is larger than unity. Various Schottky diode electrical parameters are obtained here from temperature dependent capacitance–voltage (C–V) measurements. The function of Au/TMO/Au Schottky diode system is well explained from current–voltage (I–V) characteristics study. Ferroelectric-like hysteretic behaviour is observed at and above room temperature from non-ferroelectric TMO. Presence of defect states at TMO interface layer dominates the charge conduction phenomenon. Negative magnetodielectric effect arises in heterogeneous TMO sample due to the effect of magnetic field on Maxwell–Wagner space charge at the interface. The thermionic current–voltage (I–V) characteristics of the Au/TMO/Au Schottky diode have been measured within the voltage range ± 40 V. Ferroelectric type hysteretic behaviour is observed in non-ferroelectric TMO sample.

Influence of Charge Transport Layers on Capacitance Measured in Halide Perovskite Solar Cells

Summary Capacitance-based techniques have been used to measure the electrical properties of halide perovskite solar cells (PSCs) such as defect activation energy and density, carrier concentration, and dielectric constant, which provide key information for evaluating the device performance. Here, we show that capacitance-based techniques cannot be used to reliably analyze the properties of defects in the perovskite layer or at its interface, because the high-frequency capacitance signature is due to the response of charge carriers in the hole-transport layer (HTL). For HTL-free PSCs, high-frequency capacitance can be considered as the geometric capacitance for analyzing the dielectric constant of the perovskite layer because there is no trapping and de-trapping of charge carriers in the perovskite layer. We further find that the low-frequency capacitance signature can be used to calculate the activation energy of the ionic conductivity of the perovskite layer, but the overlapping effects with charge transport materials must be avoided.

Solid-State Carbon-Doped GaN Schottky Diodes by Controlling Dissociation of the Graphene Interlayer with a Sputtered AlN Capping Layer.

Carbon-doped GaN (GaN:C) Schottky diodes are prepared by controlling the destruction status of the graphene interlayer (GI) on the substrate. The GI without a sputtered AlN capping layer (CL) was destroyed because of ammonia precursor etching behavior in a high-temperature epitaxy. The damaged GI, like nanographite as a solid-state carbon doping source, incorporated the epitaxial growth of the GaN layer. The secondary ion mass spectroscopy depth profile indicated that the carbon content in the GaN layer can be tuned further by optimizing the sputtering temperature of AlN CL because of the better capping ability of high crystalline quality AlN CL on GI being achieved at higher temperature. The edge-type threading dislocation density and carbon concentration of the GaN:C layer with an embedded 550 °C-grown AlN CL on a GI substrate can be significantly reduced to 2.28 × 109 cm-2 and ∼2.88 × 1018 cm-3, respectively. Thus, a Ni-based Schottky diode with an ideality factor of 1.5 and a barrier height of 0.72 eV was realized on GaN:C. The series resistance increased from 28 kΩ at 303 K to 113 kΩ at 473 K, while the positive temperature coefficient (PTC) of series resistance was ascribed to the carbon doping that induced the compensation effect and lattice scattering effect. The decrease of the donor concentration was confirmed by temperature-dependent capacitance-voltage (C-V-T) measurement. The PTC characteristic of GaN:C Schottky diodes created by dissociating the GI as a carbon doping source should allow for the future use of high-voltage Schottky diodes in parallel, especially in high-temperature environments.

Electrical and optical characterization of CdTe solar cells with CdS and CdSe buffers—A comparative study

A study is reported comparing the electrical and optical properties of CdTe solar cells, prepared using CdS and CdSe buffer layers, to investigate defects in the bulk and interface, carrier transport, and recombination. Temperature dependent capacitance–voltage measurement and admittance spectroscopy were used to extract carrier concentration, resistivity, charge carrier mobility, and their temperature dependence. The authors identify the presence of two defect signatures corresponding to carrier freeze-out and the formation of a Schottky back-contact barrier. The back-contact barrier height (≈300 meV) extracted from the temperature dependent current density–voltage (JVT) experiment was confirmed by conventional admittance spectroscopy. The activation energies of mobility (resistivity) are 101.2 ± 2.5 meV (92.6 ± 2.3 meV) and 84.7 ± 2.7 meV (77.6 ± 4.5 meV) for CdS and CdSe buffer layers, respectively. Intensity dependent photoluminescence analysis demonstrates that the CdSe/CdTe device exhibits lower radiative efficiency than the CdS/CdTe device. This confirms the presence of higher defects in the CdSe/CdTe device corroborated by temperature dependent VOC analysis. The comparative electrical and optical analysis provides insight into improving the performance of CdTe solar cell device by selenization.

Mechanism of phosphorus passivation of near-interface oxide traps in 4H–SiC MOS devices investigated by CCDLTS and DFT calculation

Interfacial charge trapping in 4H–SiC MOS capacitors with P doped SiO2 or phospho-silicate glass (PSG) as a gate dielectric has been investigated with temperature dependent capacitance–voltage measurements and constant capacitance deep level transient spectroscopy (CCDLTS) measurements. The measurements indicate that P doping in the dielectric results in significant reduction of near-interface electron traps that have energy levels within 0.5 eV of the 4H–SiC conduction band edge. Extracted trap densities confirm that the phosphorus induced near-interface trap reduction is significantly more effective than interfacial nitridation, which is typically used for 4H–SiC MOSFET processing. The CCDLTS measurements reveal that the two broad near-interface trap peaks, named ‘O1’ and ‘O2’, with activation energies around 0.15 eV and 0.4 eV below the 4H–SiC conduction band that are typically observed in thermal oxides on 4H–SiC, are also present in PSG devices. Previous atomic scale ab initio calculations suggested these O1 and O2 traps to be carbon dimers substituted for oxygen dimers (CO=CO) and interstitial Si (Sii) in SiO2, respectively. Theoretical considerations in this work suggest that the presence of P in the near-interfacial region reduces the stability of the CO=CO defects and reduces the density of Sii defects through the network restructuring. Qualitative comparison of results in this work and reported work suggest that the O1 and O2 traps in SiO2/4H–SiC MOS system negatively impact channel mobility in 4H–SiC MOSFETs.

Al2O3/ $\beta $ -Ga2O3(-201) Interface Improvement Through Piranha Pretreatment and Postdeposition Annealing

In this letter, we report on the improvement of atomic layer deposited (ALD) Al2O3/ $\beta $ –Ga2O3 (-201) interface quality through piranha pretreatment and postdeposition annealing (PDA). The high quality interface is verified via the temperature dependent capacitance–voltage ( $C$ – $V$ ) and photo-assisted (deep UV) $C$ – $V$ measurements, considering its ultra wide bandgap of 4.8 eV for $\beta $ -Ga2O3. A low $C$ – $V$ hysteresis of 0.1 V from the measurement frequency of 1 kHz to 1 MHz is obtained, compared with the hysteresis of 0.45 V without piranha optimization. An average interface trap density $({\mathrm{ D}}_{\mathrm {it}})$ of $2.3 \times 10^{11}$ cm $^{\mathrm {-2}}\cdot $ eV $^{\mathrm {-1}}$ is extracted from the photo $C$ – $V$ measurements. Piranha pretreatments and PDA turn out to be an effective way to improve the ALD Al2O3/ $\beta $ –Ga2O3 (-201) interface for future high quality Ga2O3 metal–oxide–semiconductor field-effect transistors.

Defect characterization in co-evaporated Cu2ZnSnSe4 thin film solar cell

Cu2ZnSnSe4 (CZTSe) solar cell fabricated by selenization of co-evaporated Cu–Zn–Sn–Se precursor thin film exhibited 6.2% conversion efficiency. Defects in the solar cell were investigated by temperature-dependent capacitance-voltage and admittance spectroscopy. Capacitance-voltage measurements showed that the p-type conductivity of CZTSe absorber layer was mainly attributed to two acceptor levels with activation energy of 0.02 eV and 0.11 eV. The admittance spectra exhibited capacitance steps that might have originated from a defect level with activation energy of 0.16 eV. The effects of these defects on the solar cell were discussed.

Optical absorption of the anthracene and temperature-dependent capacitance–voltage characteristics of the Au/anthracene/n-Si heterojunction in metal–organic-semiconductor configuration

An anthracene film has been deposited on an n-type silicon to fabricate an Au/anthracene/n-Si junction device. The band gap of the anthracene film has been determined from the optical measurement as Eg=1.65eV. After the fabrication of the Au/anthracene/n-Si junction device, temperature dependent capacitance–voltage characteristics in the range of 160–300K were studied to obtain the junction parameters of the device. The diffusion potential, barrier height, Fermi energy level and donor concentration parameters have been determined from the linear 1/C2–V curves with reverse bias at all temperatures. Both Fermi energy level and the barrier height increased with the increasing temperature. Temperature-dependence of the barrier height has been attributed to inhomogeneous barrier, traps and interface states. The ionized donor concentrations have varied with the temperature in an unsystematic manner due to the trapping/de-trapping of the charges at various temperatures.

Effect of temperature on the current (capacitance and conductance)–voltage characteristics of Ti/n-GaAs diode

In this study, Ti/n-GaAs Schottky barrier diode has been fabricated by DC magnetron sputtering. The current–voltage, capacitance–voltage, and conductance–voltage characteristics of Ti/n–GaAs diode have been investigated in the temperature range of 80–320 K. The ideality factor and barrier height values have been calculated from the forward current–voltage characteristics. The variation of the diode parameters with the sample temperature has been attributed to the presence of the lateral inhomogeneities of the barrier height. The temperature dependent capacitance–voltage characteristics have been measured to calculate the carrier concentration, diffusion potential, barrier height, and temperature coefficient of the barrier height (α = −0.65 meV K−1). The fact that the temperature coefficient of the barrier height changes from metal to metal has been ascribed to the chemical nature of the contact metal or metal electronegativity.

Impact of copper back contact in CdTe solar cells: study of defects by temperature-dependent capacitance–voltage measurements

Copper diffusion from back contact creates semishallow and deep-level defects in n+-CdS/p-CdTe solar cells. This study analyzes the impact of copper as a function of annealing temperatures during back contact formation. The observed defect levels, formed after copper diffusion, were identified by employing the temperature-dependent capacitance–voltage (C-V) characteristics at reverse bias in the dark. Theoretical background involving recombination centers, defect density and the role of impurity defects (copper-related defects) suggests that the temperature-dependent C-V profiling is a suitable technique to investigate the copper-related defects. Samples, annealed at 160°C for 30 min, show only one energy level, whereas samples annealed at 280ºC for 30 min reveal two distinct deep levels. From the reported observations, the trap levels were identified as copper-related defects. Variation in annealing temperature can impact the defect formation process: substitutional impurities of copper (160°C) and deep levels (280°C).

Temperature Dependence of Electrical Characterization in n+ - CdS/ p - CdTe Thin Film Solar Cells – Study of Shallow/Deep Defects

ABSTRACTFor CdTe there is no real distinction between defects and impurities exists when non-shallow dopants are used. These dopants act as beneficial impurities or detrimental carrier trapping centers. Unlike Si, the common assumption that the trap energy level Et is around the middle of the band-gap Ei, is not valid for thin film CdTe. Trap energy levels in CdTe band-gap can distributed with wide range of energy levels above EF. To identify the real role of traps and dopants that limit the solar cell efficiency, a series of samples were investigated in thin film n+-CdS/p-CdTe solar cell, made with evaporated Cu as a primary back contact. It is well known that process temperatures and defect distribution are highly related. This work investigates these shallow level impurities by using temperature dependent current-voltage (I-V-T) and temperature dependent capacitance-voltage (C-V-T) measurements. I-V-T and C-V-T measurements indicate that a large concentration of defects is located in the depletion region. It further suggests that while modest amounts of Cu enhance the cell performance by improving the back contact to CdTe, the high temperature (greater than ∼100°C) process condition degrade device quality and reduce the solar cell efficiency. This is possibly because of the well-established Cu diffusion from the back contact into CdTe. Hence, measurements were performed at lower temperatures (T = 150K to 350K). The observed traps are due to the thermal ionization of impurity centers located in the depletion region of p-CdTe/n+-CdS junction. For our n+-CdS/p-CdTe thin film solar cells, hole traps were observed that are verified by both the measurement techniques. These levels are identical to the observed trap levels by other characterization techniques.

Effects of N Incorporation on Electron Traps at SiO<sub>2</sub>/SiC Interfaces

Temperature dependent capacitance-voltage (C-V) and constant capacitance transient spectroscopy (CCDLTS) measurements have been performed to investigate the role of N in improving the transport properties of 4H-SiC MOS transistors. The higher channel mobility in the N pre-implanted transistors is due at least in part to activation of a small fraction of the implanted N near the SiO2/SiC interface as donors in SiC during oxidation, thus reducing the effects of interface trapping. In addition, the absence of oxidation-induced near-interface defects, which were observed in NO-annealed capacitors, may contribute to the improved mobility in N pre-implanted transistors.

Experimental evidence for the correlation between the weak inversion hump and near midgap states in dielectric/InGaAs interfaces

Temperature dependent capacitance–voltage (C-V) and conductance-voltage (G-V) measurements were performed to obtain activation energies (EA) for weak inversion C-V humps and parallel conductance peaks in Al2O3/InGaAs and Si3N4/InGaAs gate stacks. Values of 0.48 eV (slightly more than half of the band gap of the studied In0.53Ga0.47As) were obtained for EA of both phenomena for both gate dielectrics studied. This indicates an universal InGaAs behavior and shows that both phenomena are due to generation-recombination of minority carriers through near midgap located interface states. The C-V hump correlates with the interface states density (Dit) and can be used as a characterization tool for dielectric/InGaAs systems.

Temperature-dependent capacitance–voltage biasing of the highly tunable TlGaTe2 crystals

The temperature effects on the capacitance–voltage characteristics as well as the room temperature capacitance–frequency characteristics of TlGaTe2 crystals are investigated. A very wide range of linearly varying tunable capacitance from 6.0μF to 60pF was recorded. The capacitance–voltage characteristics, being recorded in the temperature range of 290–380K, revealed a linear increase in the build in voltage associated with exponential decrease in the density of non-compensated ionized carriers with increasing temperature. The high temperature (up to 380K) biasing ability, the linear tunability and the high dielectric constant values (∼103) make the TlGaTe2 crystals applicable in microelectronic components.