Technology Computer-aided Design Research Articles

METODOLOGÍA COMBINADA DE SIMULACIÓN PARA UNA CARACTERIZACIÓN COMPLETA DE LOS EFECTOS DE LA RADIACIÓN IONIZANTE EN DISPOSITIVOS DE DETECCIÓN

Ionizing radiation detection devices have been widely used in recent years in various applications and experimental fields, such as high-energy physics, nuclear physics, and medical imaging. Detailed description of their operational properties and their characterization by means of numerical modelling, as simulations, are key issue to understand the characteristics of radiation detectors in terms of efficiency, resolution and signal-to-noise ratio, since they allow optimising parameters that will be further used. The modelling processes, as the simulations, are routinely carried out using various tools, like Monte Carlo approaches, for instance: PENELOPE, FLUKA or GEANT4 are used to study the interaction of the radiation with the detector accounting for the whole physical processes. However, transporting electron/hole pairs, as generated through the device sensor to conform the corresponding electronic signals uses tools based on the finite element method, such as TCAD (Technology Computer Aided Design), which are developed mainly to help the microelectronics industry to design products. Usually, modelling approaches for radiation transport and electronic signal production are not integrated, thus performing the simulation process by splitting the problem into successive independent phases. Within this framework, the present study proposes, implements, and reports on a novel methodology that allows combining the two approaches aimed at integrating the complete simulation, thus achieving astep-by-step integrated modelling flow to describe the interaction of ionizing radiation with the sensor along with thetransport of the generated charge to the photodiodes and, finally, to the generation of electronic signals.

Improving the accuracy of ion implantation simulations through the use of DFT-MD methodology

Ion implantation is a crucial process in the fabrication of semiconductor devices, but accurately predicting the impurities distribution in the low energy range is still challenging. The widely used method to simulate this process is molecular dynamics with recoil interaction approximation (RIA-MD), which uses the translational method to replace traditional periodic boundary conditions. However, this approach leads to accuracy loss due to the simplification of atom-atom interactions and bulk crystal properties. Our study presents a method to simulate the impurity distribution after ion implantation at low energy, which combines all-electron density-functional theory (DFT) and full molecular dynamics (MD). Unlike the RIA-MD method, DFT-MD method calculates the movements of all energetic ions and simulates the whole bulk crystal properties. Thus, it provides a more realistic representation of atom-atom interactions. We used not only the experimental values reported by references but also the experimental value measured by actual ion implantation technology samples. This enabled us to make a more accurate comparison between the DFT-MD and RIA-MD methods. Specifically, the dopant profiles and amorphous thickness obtained using the DFT-MD method were found to be in good agreement with experimental data. These findings demonstrate the effectiveness of our method and highlight its potential to advance the field of ion implantation simulation. Moreover, our method has the potential to be useful in developing atomic-scale technology computer-aided design (TCAD) tools, as well as in other fields of research that require accurate ion implantation simulations.

(Invited) Simulations of Ultra-Scaled Electronic Devices with a Novel Flexible Nano-TCAD Nano-Electronic Simulation Software (NESS) Environment

Simulation of conventional and emerging electronic devices using Technology Computer Aided Design (TCAD) tools has been an essential part of the semiconductor industry as well as academic research. Computational efficiency and accuracy of the numerical modeling are the key criteria on which quality and utility of a TCAD tool is ascertained. Further, the ability of the tool to incorporate different modeling paradigms and to be applicable to a wide range of device architectures and operating conditions is essential.In this talk, I will provide an overview of the new device simulator NESS (Nano-Electronic Software Simulator) developed at Device Modelling Group at University of Glasgow. NESS is a fast, modular software with its own structure and mesh generators, and contains different modules for classical, semi-classical, and quantum transport solvers, mobility calculation, kinetic Monte-Carlo etc. NESS can simulate numerous device architectures such as nanowire and bulk transistors, tunnelling field effect transistors (TFET) and resonant tunnelling diodes. Moreover, NESS accounts for various sources of statistical variability in nano-size electronic devices and it can perform statistical simulations for thousands microscopically different devices.

Investigation of In0.7Ga0.3As/Ga0.5As0.5Sb-Based Heterojunction TFET with Ferroelectric Gate Dielectric for Performance and Reliability

This paper investigates In[Formula: see text]Ga[Formula: see text]As/Ga[Formula: see text]As[Formula: see text]Sb-based Heterojunction Tunnel Field Effect Transistor with ferroelectric dielectric as stack layer, namely Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) for the first time for performance and reliability. Ferroelectric gate dielectric has been inculcated in the device design in addition to the doping of Ga[Formula: see text]As[Formula: see text]Sb in the source region and In[Formula: see text]Ga[Formula: see text]As in the drain region, respectively. The performance of the proposed device is quantified in terms of DC electrical parameters and short channel parameters. The reliability analysis of the proposed device has been carried out in terms of influence of variations of interface trap charges, gate-source overlap length and temperature on the device transfer characteristics. From the simulation results, it can be manifested that the proposed device presents superior DC electrical characteristic and reduced short channel effects as compared to the GaSb/Si Dual Material Stacked Double Gate Heterojunction TFET (GaSb/Si DMSDG-HJTFET), under the influence of group III–V materials and ferroelectric gate dielectric. In addition to this, the proposed device depicts elevated immunity to presence of interface trap charges at the interface, variations in gate-source overlap length and temperature variations as well. The implication of TiO2 as dielectric stack over SiO2 provides exceptional capacitive coupling at the interface and thus assists in the improvement of electrical characteristics of the device by enhancing the electric field. The outcome of the simulation results presents that Ga[Formula: see text]As[Formula: see text]Sb/In[Formula: see text]Ga[Formula: see text]As-based Ferroelectric Dual Material Stacked Double Gate Heterojunction TFET (FDMSDG-HJTFET) can prove to be a competitive alternative for high performance applications with improved reliability. The design and simulation of the proposed device structure has been executed using technology computer-aided design (TCAD) tool.

Impact of heavy ions on a-Si:H/PolySi bilayer thin film transistors with Schottky barrier source and drain based on Nickel Silicide

This study investigates the influence of heavy ion irradiation on thin film transistors (TFTs) based on an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. Through the use of Technology Computer-Aided Design (TCAD) simulations, we analyze the impact on device performance. We examine the ambipolar device characteristics by varying the thickness of the active layer (Poly-Si) and studying the corresponding physics. Our results reveal that reducing the active layer thickness from 140 to 80 nm decreases the magnitude of the threshold voltage (|VT|) for both nMOS and pMOS operating voltages. Additionally, the subthreshold slope is reduced for both nMOS and pMOS as the active layer thickness is decreased from 140 to 80 nm.Further, we investigated the transient response of the drain current to heavy ion irradiation in the sensitive regions across the Schottky barrier-based source and drain. We specifically analyze the phenomenon of bipolar amplification for various Linear Energy Transfer (LET) values, ranging from 0.1 MeV cm2/mg to 100 MeV cm2/mg. Our findings indicate that increasing the LET values from 0.1 MeV cm2/mg to 100 MeV cm2/mg results in amplified bipolar behavior and a drain current overshoot of over 10 % for both pMOS and nMOS operating voltages. To summarize, this work highlights the effects of heavy ion irradiation on TFTs with an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. The study explores the influence of active layer thickness on device characteristics and demonstrates the transient response of drain current under different LET values. These findings contribute to a better understanding of the behavior and performance of TFTs subjected to heavy ion irradiation.

Negative Capacitance Dual-Gated ISFETs as Ultra-Sensitive pH Sensors.

Ion-sensitive field-effect transistors (ISFETs) are promising candidates for next-generation pH sensors, enabling highly sensitive and label-free biomolecular and chemical detection. Emerging FETs based on the negative capacitance (NC) effect offer steep-subthreshold switching and higher drive current simply by integrating a ferroelectric (FE) material into the gate stack. Here, we propose a novel NC dual-gated ISFET (NC-DG-ISFET)-based pH sensor, with FE layers integrated into both the top and the bottom gate stacks. The current and voltage sensitivities of the proposed device are extracted from its transfer characteristics, obtained by combining the numerical solutions of the one-dimensional (1D) Landau-Khalatnikov (L-K) equation with three-dimensional (3D) technology computer-aided design (TCAD) simulations. Results show that the NC-DG-ISFET can surpass the sensitivity of some of the state-of-the-art DG-ISFET pH sensors. The inclusion of the FE layers into the gate stacks of a baseline DG-ISFET leads to 51% reduction in subthreshold swing (SS), causing a 5× increase in current sensitivity (SI) in the subthreshold region of operation and a 2× increase in voltage sensitivity (SV). The influence of channel thickness and channel length on the sensor performance is also invesitgated. The findings presented here provide a new pathway to leverage the steep-switching behavior of NCFETs for the next generation of highly sensitive and label-free DG-ISFET pH sensors.

Demonstration of a Frequency Doubler Using a Tunnel Field-Effect Transistor with Dual Pocket Doping

In this study, a frequency doubler that consists of a tunnel field-effect transistor (TFET) with dual pocket doping is proposed, and its operation is verified using technology computer-aided design (TCAD) simulations. The frequency-doubling operation is important to having symmetrical current characteristics, which eliminate odd harmonics and the need for extra filter circuitry. The proposed TFET has intrinsically bidirectional and controllable currents that can be implemented by pocket doping, which is located at the junction between the source/drain (S/D) and the channel region, to modify tunneling probabilities. The source-to-channel (ISC) and channel-to-drain currents (ICD) can be independently changed by managing each pocket doping concentration on the source and drain sides (NS,POC and ND,POC). After that, the current matching process was investigated through NS,POC and ND,POC splits, respectively. However, it was found that the optimized doping condition achieved at the device level (namely, a transistor evaluation) is not suitable for a frequency doubler operation because the voltage drop generated by a load resistor in the frequency doubler circuit configuration causes the currents to be unbalanced between ISC and ICD. Therefore, after symmetrical current matching was performed by optimizing NS,POC and ND,POC at the circuit level, it was clearly seen that the output frequency was doubled in comparison to the input sinusoidal signal. In addition, the effects of the S/D and pocket doping variations that can occur during process integration were investigated to determine how much frequency multiplications are affected, and these variations have the immunity of S/D doping and pocket doping length changes. Furthermore, the impact of device scaling with gate length (LG) variations was evaluated. Based on these findings, the proposed frequency doubler is anticipated to offer benefits for circuit design and low-power applications compared to the conventional one.

The Structural Performance of a Novel Double‐Stacked Heterogeneous Gate Heterojunction Tunneling Field‐Effect Transistor

In this work, an original Si/SiGe heterojunction tunneling field‐effect transistor which has a double‐stacked heterogeneous oxide gate (HfO2/Al2O3) structure (DSG–HJ–TFET) is designed and investigated by Sentaurus technology computer aided design (TCAD) simulation software. To ensure good interface quality, a stacked oxide gate dielectric of Al2O3 and HfO2 is proposed. The on‐state current (Ion) is increased though improving the carrier mobility degradation caused by the poor quality of interface between the high‐κ dielectric and semiconductor. Moreover, a heterojunction with SiGe (source)/Si (channel) and pocket layer which is inserted between the source region and the channel is adopted to reduce the tunneling barrier and improve the Ion. Therefore, the higher Ion is obtained by the proposed DSG–HJ–TFET. In the simulation results, it is shown that Ion of DSG–HJ–TFET is increased by three orders of magnitude compared with that of the conventional high‐κ gate dielectric TFET structure. In addition, the off‐state current (Ioff) of 4.91 × 10−11 μA μm−1, the minimum subthreshold swing of 14 mV dec−1, the Ion/Ioff ratio of 1.13 × 1012, transconductance of 260 μS μm−1, fT of 49.8 GHz, and gain bandwidth product (GBW) of 7.2 GHz are obtained. The propose DSG–HJ–TFET is favored in ultralow‐power applications for the rather good performance.

A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories

In this paper, a novel read scheme using gate-induced drain leakage (GIDL) current is proposed to suppress read disturbance in 3-D NAND flash memories. The proposed read scheme is demonstrated through the technology computer-aided design (TCAD) simulation. In the selected string, GIDL current is not generated due to the low potential difference. On the other hand, in the unselected string, holes are accumulated under the selected cell and potential of the selected cell is enhanced due to the GIDL current before the read operation. The potential differences between the selected and adjacent cells are decreased and maximum electric field (Em) is decreased. Therefore, soft programming in the selected cell during the read operation is decreased and hot carrier injection (HCI) between selected and adjacent cells is reduced completely. The proposed read scheme can be applied to high stacked WL layers over 200 layers.

Investigation of graded channel effect on analog/linearity parameter analysis of junctionless surrounded gate graded channel MOSFET

Linearity analysis of nanoscale devices is a vital issue as nonlinearity behavior is exhibited by them when employed in circuits for microwave and RF applications. In this work, a junctionless surrounded gate-graded channel MOSFET (JLSGGC MOSFET) is investigated thoroughly to analyze its linearity performance with the help of ATLAS tool of technology computer-aided design. The proposed device is compared systematically with the conventional junstionless surrounded gate MOSFET(JLSG MOSFET) to investigate their linearity. To evaluate the linearity, the figure of merits such as higher-order transconductance (Gm1, Gm2), intercept points(VIP2, VIP3, IIP3), IMD3 and 1 dB—compression point(P1 dB) are considered. The linearity of our proposed device improves by 35.5% in view of the compression point in comparison to JLSG MOSFET before the threshold voltage region of operation. The simulation results reveal a substantial enhancement in the linearity performance of the JLSGGC MOSFET. The improved linearity behavior of JLSGGC MOSFET makes it suitable for wireless RF and system-on-chip applications.Analog/RF performance is studied in terms of intrinsic gain (Gm/Gds), cut-off frequency (fT),maximum frequency of oscillation (fmax).Improved analog/RF performances of JLSGGC MOSFET suggests its applications in high frequency operating range.

Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory.

Electrical characteristics with various program temperatures (TPGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the TPGM up to 120 °C and the read temperature (TREAD) at 30 °C are used to analyze the influence of grain boundaries (GB) on the bit line current (IBL) and threshold voltage (VT). The VT shift in the E-P-E pattern is successfully decomposed into the charge loss (ΔVT,CL) component and the poly-Si GB (ΔVT,GB) component. The extracted ΔVT,GB increases at higher TPGM due to the reduced GB potential barrier. Additionally, the ΔVT,GB is evaluated using the Technology Computer Aided Design (TCAD) simulation, depending on the GB position (XGB) and the bit line voltage (VBL).

Development of a Charge-Multiplication CMOS Image Sensor Based on Capacitive Trench for Low-Light-Level Imaging

This paper presents an electron multiplication charge coupled device (EMCCD) based on capacitive deep trench isolation (CDTI) and developed using complementary metal oxide semiconductor (CMOS) technology. The CDTI transfer register offers a charge transfer inefficiency lower than 10−4 and a low dark current o 0.11nA/cm2 at room temperature. In this work, the timing diagram is adapted to use this CDTI transfer register in an electron multiplication mode. The results highlight some limitations of this device in such an EM configuration: for instance, an unexpected increase in the dark current is observed. A design modification is then proposed to overcome these limitations and rely on the addition of an electrode on the top of the register. Thus, this new device preserves the good transfer performance of the register while adding an electron multiplication function. Technology computer-aided design (TCAD) simulations in 2D and 3D are performed with this new design and reveal a very promising structure.

Double-gated ferroelectric-gate field-effect-transistor for multi-bit content-addressable memories

In this study, we proposed a novel multi-bit content addressable memory (MCAM) cell based on one single double-gated ferroelectric-gate FET (DG-FeFET). Baseline DG-FeFET has been modeled, and the parameters are calibrated with experimental results by technology computer aided design (TCAD). Thanks to the pairing opposite ferroelectric states of the top/bottom gate (TG/BG) and pairing opposite searching voltages applied to TG and BG, MCAM functions with one DG-FeFET can be realized. The corresponding writing and searching operations are investigated in detail by the TCAD Sentaurus model. In addition, it is clarified that reducing the coupling effect of top and bottom channel by appropriately increasing the body thickness (Tbody) can boost the mismatch/match ratio. The proposed MCAM cell with one single DG-FeFET is promising for ultra-high-density computing systems.

An analytical interpretation of the memory window in ferroelectric field-effect transistors

In this study, we present an analytical equation for describing the memory window of ferroelectric field-effect transistors (FeFETs). The analytical equation is derived based on the effect of oxide charge on the threshold voltage shift of the field-effect transistor and can be expressed by simpler parameters, such as the quantity of polarization switching and trapped charge. We demonstrate that the derived equation is in quantitative agreement with the results of the numerical calculations using a technology computer-aided design simulation tool, which confirms the validity of the equation. Our results show that the analytical equations provide an accurate and practical description of the memory window for FeFETs with various structures.

Sensitivity analysis of TMD TFET based photo-sensor for visible light detection: A simulation study

This paper reports the sensitivity analysis of double gate TFET using the Transition Metal Di chalcogenide (TMD) material in photo sensitive region with the help of technology computer aided design (TCAD) simulator tool. The sensitivity analysis elaborates the significance of TMD material for optical applications. The photo sensitivity analysis is exhibited for the variation in wavelength (λ) of incident light under the visible range of spectrum. Furthermore, we have executed the performance of photo sensor by varying the position of illumination window. Result reveals that sensitivity, responsivity, and quantum efficiency of sensor are improved at λ = 320 nm. The maximum value of signal to noise ratio (SNR) and responsivity (R) are 63.2 dB and 106, respectively, under the visible range. This TMD material based TFET photo-sensor will be useful for the next generation low power highly sensitive optical devices.

TCAD simulations of internal amplification in high purity germanium detectors

Simulations of internal amplification processes in high purity germanium (HPGe) detectors for gamma radiation are presented. The Synopsys Sentaurus Technology Computer-Aided Design (TCAD) package was employed to study conditions favourable to charge multiplication within volume of the detector. The physics model was developed, and validated where possible against known results from existing literature. The model was then applied to a new detector and a systematic study of the measurable parameters influencing charge collection and electric field profile was performed. Evidence of the internal amplification in the developed HPGe detector model was demonstrated at 4 kV bias voltage with anode diameter below 100 μm, corresponding to 16 kV/cm electric field and when an additional dopant with concentrations >5×1010cm−3 under the anode implanted. These effects were also simulated and observed in silicon detectors, giving additional confidence in the validity of the findings for germanium, presented in this work.

Investigating the effects of doping gradient, trap charges, and temperature on Ge vertical TFET for low power switching and analog applications

Influence of Gaussian doping in transistor regions, doping gradient step size (σ), interface trap charges (ITC), and temperature on DC, Analog, and Linearity performance of Ge-Vertical Tunnel FET (VTFET) is explored using Technology Computer-Aided Design. The DC transfer/output characteristics, ION/IOFF ratio, sub-threshold swing(S); and Analog/RF parasitic capacitances (Cgg, Cgs, and Cgd), transconductance (gm), cut-off frequency (ft), Transit time, efficiency, are examined with Doping Gradient in source & drain, σ variance up to 25 nm, and ITC variation from 1010–1012 cm−2 at Al2O3/Ge interface. Further, linearity parameters, such as gm3, VIP2, VIP3, IMD3, IIP3 &CP1-dB are estimated for optimum Ge-VTFET. For reliability analysis, Ge-VTFET is inspected with temperature deviation from 250 K to 375 K. The proposed Ge-VTFET with the doping gradient in drain and σ of 25 nm revealed excellent performance such as low S ∼ 58 mV/dec, high ION/IOFF ratio ∼ 3 × 105, gm ∼ 6.8 µS, ft ∼ 3.96 GHz, and outstanding reliability even under ITC and temperature deviations, proved Ge-VTFET to be an exceptional contender for low-power switching & analog applications.

Simulation study on quantum dot formation of double-qubit-Si-MOS device

Silicon quantum dots (QDs) are essential physical carriers of quantum bits (qubits) in quantum computing. However, their extremely small size renders them highly sensitive to both the fabrication process and surrounding environment. Accuracy and stability must be carefully considered. In this study, we propose a double gate QD device model based on silicon metal-oxide-semiconductor (Si-MOS) for the generation of spin qubits. Using a Technology Computer Aided Design (TCAD) simulation, we investigated the impact of device dimensions, including oxide layer thickness, channel length, and spacer length, on the QD structure. Additionally, we examined the effects of the temperature and interface trap concentration on QD formation. An equivalent circuit model was employed to assess the charging energy (Ec) of QDs. Our results demonstrate that by appropriately adjusting these parameters, it is possible to achieve a QD structure with a wide level spacing and small size capable of accommodating as few as four electrons. Furthermore, we calculated an Ec of 33 meV for the QDs.

Characterization of Single Event Effect in a Radiation Hardened Programmable Read-Only Memory in a 130 nm Bulk CMOS Technology

The concept of memory that can only be read but cannot be changed seems strange at first. In reality, it is found that it has great application potential, such as the processor with a fixed purpose, the initial set value of the microprocessor BIOS, and these data are stored in Programmable Read-Only Memory (PROM) to quickly realize system functions. The PROM storage content is fixed, greatly simplifying his design. The radiation of space particles is the main factor causing the failure of the electronic system of spacecraft. The PROM storage array of the space electronic system is the most basic guarantee for the normal operation of the electronic system. The chip adopts domestic 130 nm standard technology of Complementary Metal Oxide Semiconductor (CMOS), Muller-C digital filter is used in the peripheral subsystem of PROM storage array, and the core cell uses Dual Interlocked Cell (DICE) and ring gate and other radiation hardening technologies to design a 32Kx8bit radiation resistant asynchronous programmable PROM. Pre-silicon of devices was verified by Technology Computer Aided Design (TCAD), and post silicon radiation verification was completed through radiation experiment. The post silicon radiation experiment showed that the total ionizing Dose (TID) capacity of the PROM chip was ≥100 Krad (Si), the critical value of single event upset (SEU) was ≥37.1 MeV·cm2/mg, the critical value of single event latch up was ≥98 MeV·cm2/mg, meeting the life requirements of the initial value storage of aerospace electronic systems. These performances ensure the reliable operation of the space electronic system after restart.

Fabrication and performance of highly stacked GeSi nanowire field effect transistors

AbstractHorizontal gate-all-around field effect transistors (GAAFETs) are used to replace FinFETs due to their good electrostatics and short channel control. Highly stacked nanowire channels are widely believed to enhance drive current of these devices and improve overall transistor density due to their small footprint. Here we demonstrate the fabrication and characterization of nanowire FETs with stacked 16 Ge0.95Si0.05 nanowires and stacked 12 Ge0.95Si0.05 nanowires without parasitic channels. The device has the high on current (ION) of 190 μA per stack (9400 μA/μm per channel footprint) at overdrive voltage (VOV) = drain-source voltage (VDS) = 0.5 V and the high maximum transconductance (Gm,max) of 490μS (24000μS/μm) at VDS = 0.5 V among reported Si/Ge/GeSi 3D nFETs. Note that the transistor performance can be evaluated by the delay, which is depicted as CV/I. If the transistor ION is improved, the delay of standard cell can be reduced, leading to faster operation of the circuit. The subthreshold slope reduction and ION/IOFF improvement are achieved by the parasitic channel removal. In technology computer aided design (TCAD) simulation, the wrap around contacts are useful to reduce the current difference between the channels. With the proper design of transistor height, the gate delay can be also improved.