Technology Computer-aided Design Simulation Research Articles

TCAD Calibration at Cryogenic Temperatures for CMOS Image Sensor Simulations

A simple calibration method is presented for the technology computer-aided design (TCAD) simulation at cryogenic temperature, with a special focus on image sensor application. Based on the principle that TCAD tools are not completely mature for cryogenic environment, a calibration is needed to perform reliable simulations. In this work, measurements and simulations of sheet resistances are used for the TCAD calibration, and an experimental verification is performed by means of the extraction of pinning voltages on JFETs and on a pixel including a pinned photodiode (PPD).

Impact of sidewall spacer materials and gate underlap length on negative capacitance double-gate tunnel field-effect transistor (NCDG-TFET)

In this study, a negative capacitance double-gate tunnel field-effect transistor (NCDG-TFET) with sidewall spacer engineering is proposed and its electrical characteristics are examined by technology computer-aided design (TCAD) simulation for lower subthreshold swing (SS) and higher on–off current ratio (Ion/Ioff) than conventional planar TFET. In detail, the dielectric constant (κ) and length of sidewall spacer (Lspc) which determine gate-to-source/drain underlap are optimized for an enhanced device performance. The simulation study shows that the sidewall spacers at source and drain underlap need to be designed differently for high Ion and low ambipolar current (Iamb). In case of source underlap, the HfO2 3 nm-Lspc can enhance outer fringing field and Ion. On the other hand, the SiO2 15 nm-Lspc at drain underlap can alleviate Iamb due to low outer fringing field. As a result, the asymmetric structure shows ∼ 1.5 times larger Ion and ∼ 4 orders lower Iamb with smaller SS and turn-on voltage (Von) than the conventional NCDG-TFET without sidewall spacer.

Readily Accessible Metallic Micro-Island Arrays for High-Performance Metal Oxide Thin-Film Transistors.

Thin-film transistors using metal oxide semiconductors are essential in many unconventional electronic devices. Nevertheless, further advances will be necessary to broaden their technological appeal. Here, a new strategy is reported to achieve high-performance solution-processed metal oxide thin-film transistors (MOTFTs) by introducing a metallic micro-island array (M-MIA) on top of the MO back channel, where the MO is a-IGZO (amorphous indium-gallium-zinc-oxide). Here Al-MIAs are fabricated using honeycomb cinnamate cellulose films, created by a scalable breath-figure method, as a shadow mask. For IGZO TFTs, the electron mobility (µe ) increases from ≈3.6 cm2 V-1 s-1 to near 15.6 cm2 V-1 s-1 for optimal Al-MIA dimension/coverage of 1.25 µm/51%. The Al-MIA IGZO TFT performance is superior to that of controls using compact/planar Al layers (Al-PL TFTs) and Au-MIAs with the same channel coverage. Kelvin probe force microscopy and technology computer-aided design simulations reveal that charge transfer occurs between the Al and the IGZO channel which is optimized for specific Al-MIA dimensions/surface channel coverages. Furthermore, such Al-MIA IGZO TFTs with a high-k fluoride-doped alumina dielectric exhibit a maximum µe of >50.2 cm2 V-1 s-1 . This is the first demonstration of a micro-structured MO semiconductor heterojunction with submicrometer resolution metallic arrays for enhanced transistor performance and broad applicability to other devices.

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

Vertical GaN diode BV maximization through rapid TCAD simulation and ML-enabled surrogate model

In this paper, two methodologies are used to speed up the maximization of the breakdown voltage (BV) of a vertical GaN diode that has a theoretical maximum BV of ∼ 2100 V. Firstly, we demonstrated a 5X faster accurate simulation method in Technology Computer-Aided-Design (TCAD). This allows us to find 50 % more numbers of high BV (>1400 V) designs at a given simulation time. Secondly, a machine learning (ML) model is developed using TCAD-generated data and used as a surrogate model for differential evolution optimization. It can inversely design an out-of-the-training-range structure with BV as high as 1887 V (89 % of the ideal case) compared to ∼ 1100 V designed with human domain expertise.

Analytical Modeling of Potential Barrier for Charge Transfer in Pinned Photodiode CMOS Image Sensors

A potential barrier is one of the most common lag sources for charge transfer in pinned photodiode (PPD) CMOS image sensors (CISs). In this article, an analytical model of the potential barrier is proposed for the PPD combined with the transfer gate (TG). Through detailed electrostatic analysis of the PPD and TG, the potential barrier is analytically expressed as a function of the doping concentrations, TG voltage, spatial dimensions, and other physical parameters. The proposed model is validated by technology computer-aided design (TCAD) simulations, and the results show that the model data are in good agreement with the TCAD simulations in terms of the magnitude and location of the potential barrier. The model can be used for the design, simulation, and optimization of PPD-based pixels in CISs to improve the charge transfer efficiency (CTE) and reduce the image lag noise.

Parasitic Oscillation Analysis of Trench IGBT During Short-Circuit Type II Using TCAD-Based Signal Flow Graph Model

The oscillation phenomenon of trench-type insulated gate bipolar transistors during short-circuit (SC) type II was investigated experimentally and theoretically. The gate resistance required to suppress oscillations decreased with an increasing collector voltage. The oscillation conditions were calculated from the signal flow graph model using the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${S}$ </tex-math></inline-formula> -parameter based on a technology computer-aided design simulation. The calculation results reproduced the locus of the collector voltage dependence of the experimentally measured gate resistance. The oscillation mechanism was investigated using the device simulation. The response of carrier density modulation at the base-drift layer boundary was found to transmit to the collector side through the electron–hole plasma region during the oscillation, indicating that the transfer characteristics of the carrier density modulation in the drift region at the specific collector voltage influence the collector voltage dependence of the SC oscillation. The influence of circuit parameters on the oscillation was also investigated. An increase in the emitter inductance suppressed the oscillations, whereas an increase in gate inductance increases oscillations.

Dynamic Avalanche Limit and Current Filamentation Onset Limit in 4H-Silicon Carbide High-Voltage Diodes

Dynamic avalanche (DA) phenomena and current filament (CF) formation are two extreme conditions observed in high-power devices, setting the maximum limit on turn-on/off current capability and di/dt in silicon (Si)-based bipolar devices. The properties of the silicon carbide (SiC) material enable devices with increased resilience for DA and CF compared with Si counterparts, and thus the safe-operating-area (SOA) limits may be extended. In this study, the limit of DA and CF in SiC-based semiconductor structures are investigated by numerical technology computer-aided design (TCAD) simulations, for different current levels, di/dt, and temperatures for high-voltage devices (e.g., 20-kV class). DA is first indicated for di/dt beyond 105 kA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> for current densities in the range of 50–1000 A/cm2, at 448 K. Similarly, stray-inductance-induced avalanche conditions are initiated above 33 kA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> , while CF is initiated for di/dt starting from 83 kA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> for current densities in the range of 8.3 kA/cm2. Moreover, the effects of the stray inductance in the main circuit loop are studied which may cause critical voltage transients during certain operating conditions. The outcome of the study may be useful to determine SOA limits and to be used as input for power electronic converter design and gate driver design for high-power electronic systems.

A Two-Dimensional Model for the Field-Plate Design of High-Voltage Transistor

The field plate (FP) is a widely adopted concept and has been commonly used for high-voltage (HV) transistors to increase the breakdown voltage without enlarging the device dimension. In this article, a 2-D mathematical equation is derived for the FP design of HV transistors which reveals the potential and the electric field distributions in the reduced-surface field (RESURF) region. From the derived mathematical model, the mechanism of the FP-induced electric field suppression for the HV transistors is completely explained as the FP can reduce the potential gradient ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E} = -\nabla \varphi $ </tex-math></inline-formula> ) caused by the dielectric thickness differences above the RESURF region. The potential and the electric field distributions of the RESURF region will change as the FP is inserted due to the dielectric thickness variations. The derived equations also explained the capacitive behaviors and quantitatively described the potential and electric field distributions in different configurations of the FP-assisted RESURF devices. The results obtained by the derived equation are found to be very much accurate compared with technology computer-aided design (TCAD) simulation results.

Radiation Hardened Millimeter-Wave Receiver Implemented in 90-nm, SiGe HBT Technology

This article presents novel radiation hardening design techniques to substantially reduce the single-event effects (SEEs) on high-frequency receivers subject to various radiations when operating in space. A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> -band (75–110 GHz) receiver front-end implemented in Global Foundry’s 90-nm silicon–germanium (SiGe) BiCMOS technology is used for studying SEE and investigating the effectiveness of the proposed techniques. Specifically, the mixer is modified to allow for different modes of operation in addition to introducing matching considerations between the mixer’s gain and switching stages. The receiver includes integrated high-frequency signal sources to provide the input radio frequency (RF) and local oscillator (LO) signals for full operation of the proposed millimeter-wave (mmW) receiver. Measurements are taken while the receiver is in normal operation (RF and LO are applied). The design techniques are carefully analyzed via extensive simulations using equivalent transient current pulses obtained from calibrated technology computer-aided design (TCAD) simulations. A two-photon absorption (TPA) pulsed laser experiment is used to induce transient currents in the silicon–germanium heterojunction bipolar transistor (SiGe HBT) circuit. Various devices within the mixer are hit from the back side through a hole in the designed printed circuit board (PCB). The propagated transients are then captured using a high-speed oscilloscope at the output of the receiver. The measurement results, supported by simulations and analysis, validate the robustness of the proposed radiation hardened receiver to SEE.

Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET

Temperature plays a decisive role in semiconductor device performance and reliability analysis. The effect is more severe in a negative capacitance (NC) transistor, as the temperature modulates the ferroelectric polarization, implicitly included by the Landau coefficients (α, β, γ) in Technology Computer Aided Design (TCAD) simulations. In this paper, through TCAD simulations, the role of varying ambient temperature is investigated in the linearity and analog/radio-frequency (RF) merits of NC-FinFET. The varying temperature modulates the carrier mobility, the semiconductor bandgap, and the Landau parameter (α). We analyzed the analog/RF and linearity metrics, such as total gate capacitance (C gg), transconductance (g m), unity gain cut-off frequency (f T), the transconductance-frequency product, gain-bandwidth product, higher-order transconductance (g m2 and g m3), voltage intercept points, third-order power intercept and intermodulation points, and 1 dB CP using well-calibrated TCAD models. Our analysis reveals that these parameters are strongly dependent on temperature and the NC span (defined by using S-curve) shrinks with the rise in temperature. Finally, a source follower and three-stage ring oscillator are designed to test the frequency compatibility of the AC simulation for varying temperatures.

Dual role of 3C-SiC interlayer on DC and RF isolation of GaN/Si-based devices

The impact of Cubic Silicon Carbide (3C-SiC) transition layer on breakdown voltage and frequency performance of GaN high electron mobility transistors is investigated. A combination of distinct material and device characterizations techniques, including Raman spectroscopy, coplanar waveguides, electrical measurements, and Technology Computer-Aided Design (TCAD) simulations, are adopted to inspect the role of the 3C-SiC interlayer. Raman spectra reveal a good quality of the 3C-SiC layer, similar to the mono-crystalline 3C-SiC spectra. A relatively low transmission loss of ∼0.16 dB/mm at 40 GHz is measured for the device with 3C-SiC layer, rather than 2.1 dB/mm for the device without 3C-SiC. In addition, a soft breakdown voltage around 1530 V at 1 μA/mm is achieved, which is three times larger compared with that of the conventional device. The failure mechanism, related to carrier injection at the nucleation layer, is not observed in the structure with the 3C-SiC layer. Instead, TCAD simulations disclose a substantial improvement of the buffer/substrate interface through the suppression of an interface current path.

Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology.

In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE). The GAA-FinFET was built using the technology computer-aided design (TCAD) simulation tool, and then, its electrical characteristics were quantitatively evaluated. The electrical characteristics of the GAA-FinFET were compared to those of conventional FinFET and nano-sheet FET (NSFET) at 7 nm or 5 nm nodes. When comparing the GAA-FinFET against the FinFET, it achieved not only better SCE characteristics, but also higher on-state drive current due to its gate-all-around device structure. This helps to improve the ratio of effective drive current to off-state leakage current (i.e., Ieff/Ioff) by ~30%, resulting in an improvement in DC device performance by ~10%. When comparing the GAA-FinFET against the NSFET, it exhibited SCE characteristics that were comparable or superior thanks to its improved sub-channel leakage suppression. It turned out that the proposed GAA-FinFET (compared to conventional FinFET at the 7 nm or 5 nm nodes, or even beyond) is an attractive option for improving device performance in terms of SCE and series resistance. Furthermore, it is expected that the device structure of GAA-FinFET is very similar to that of conventional FinFET, resulting in further improvement to its electrical characteristics as a result of its gate-all-around device structure without significant modification with respect to the processing steps for conventional FinFET.

Sensitivity study of the SiGe heterojunction bipolar transistor single event effect based on pulsed laser and technology computer-aided design simulation

The single event effect of a silicon–germanium heterojunction bipolar transistor (SiGe HBT) was thoroughly investigated. By considering the worst bias condition, the sensitive area of the proposed device was scanned with a pulsed laser. With variation of the collector bias and pulsed laser incident energy, the single event transient of the SiGe HBT was studied. Moreover, the single event transient produced by laser irradiation at a wavelength of 532 nm was more pronounced than at a wavelength of 1064 nm. Finally, the impact of the equivalent linear energy transfer of the 1064 nm pulsed laser on the single event transient was qualitatively examined by performing technology computer-aided design simulations, and a good consistency between the experimental data and the simulated outcomes was attained.

Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

The variations of single event transient (SET) pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor (FinFET) inverter chains with different driven strengths are measured at different temperatures. Three-dimensional (3D) technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature. Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk FinFET technology, resulting in the increase of SET pulse width. On the other hand, the increase of inverter driven strength will change the layout topology, which has a complex influence on the SET temperature effects of FinFET inverter chains. The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors

In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, the Sentaurus TCAD (technology computer-aided design) simulator was used. The proposed ANN model accurately and efficiently predicts currents and capacitances of devices using the five proposed key geometric parameters and two voltage biases. A variety of experiments were carried out in order to create a powerful ANN-based compact model using a large amount of data up to the sub-3-nm node. In addition, the activation function, physics-augmented loss function, ANN structure, and preprocessing methods were used for effective and efficient ANN learning. The proposed model was implemented in Verilog-A. Both a global device model and a single-device model were developed, and their accuracy and speed were compared to those of the existing compact model. The proposed ANN-based compact model simulates device characteristics and circuit performances with high accuracy and speed. This is the first time that a machine learning (ML)-based compact model has been demonstrated to be several times faster than the existing compact model.

Design of AC-coupled low gain avalanche diodes (AC-LGADs): a 2D TCAD simulation study

AC-Coupled Low Gain Avalanche Diodes (AC-LGADs) are a new type of silicon sensors which conceived for experiments at future colliders. As an evolution of the standard Low Gain Avalanche Diodes (LGADs), AC-LGADs have similar fast timing performance. The innovation is that AC-LGADs are available to provide fine temporal and spatial resolution simultaneously, thanks to two key features: AC-coupled readout through the dielectric layer and a continuous resistive n+ implant. The Institute of High Energy Physics (IHEP) High-Granularity Timing Detector group is developing its first version of AC-LGAD sensors. This paper present the impact of following parameters on AC-LGAD sensor performance: n+ dose, dielectric material and thickness, pad/pitch ratio and the distance between pad and cathode. All data are obtained from 2D Technology Computer-Aided Design (TCAD) simulations. The simulations will benefit future design and optimization.

Research of Quantized Current Effect with Work Function Variation in Tunnel-field Effect Transistor

In this paper, an investigation has been performed to analyze the relation between on-current (ISUBon/SUB) and gate work function variation (WFV) in the tunnel field-effect transistor (TFET) with help of technology computer-aided design (TCAD) simulation. Comparing the ISUBon/SUB of metal-oxide-semiconductor field-effect transistor (MOSFET) and TFET, it is observed that the quantized current level of TFET is depending on channel bias conditions and width of channel. Therefore, we analyze this current quantization within three categorizations. Firstly, the ISUBon/SUB is quantized by applied level of high gate bias (VSUBGS/SUB). At high VSUBGS/SUB, the ISUBon /SUBis quantized well following gate WF value near the source-side because the tunnel barrier is made in the specific area by junction between gate and source. However, at low VSUBGS/SUB, a lot of current levels are confirmed because almost half of the channel is affected by WFV due to the large tunneling width. Secondly, the quantized ISUBon/SUB variation by WFV is also affected by level of VSUBDS/SUB. Because the influence of the channel potential is differed by induced electron density. Finally, the ISUBon/SUB is quantized by width of device. Because, considering metal grain size, the WF value near the source-side is determined only several levels. Then, related with the width, we quantitatively analyzed the quantization of ISUBon/SUB, and based on the probability of WFVs, it is confirmed that the phenomenon of current quantization in TFET is predictable.

3-D stacked polycrystalline-silicon-MOSFET-based capacitorless DRAM with superior immunity to grain-boundary’s influence

In this paper, a capacitorless one-transistor dynamic random access memory (1 T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor with the asymmetric dual-gate (ADG) structure is designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was used within the device due to its low fabrication cost and feasibility in high-density three-dimensional (3-D) memory arrays. We studied the transfer characteristics and memory performances of the single-layer ADG 1 T-DRAMs and the 3-D stacked ADG 1 T-DRAMs and analyze the reliability depending on the location and the number of grain-boundaries (GBs). The relative standard deviation (RSD) of the threshold voltages (Vth) is depending on the location and the number of GBs. The RSDs of the single-layer ADG 1 T-DRAM and the 3-D stacked ADG 1 T-DRAM are 1.58% and 0.68%, respectively. The RSDs of retention time representing the memory performances are 54.7% and 41%, respectively. As a result of the 3-D stacked structure, the averaging effect occurs, which greatly aids in improving the reliability of the memory performances as well as the transfer characteristics of 1 T-DRAMs depending on the influence of GBs. The proposed 3-D stacked ADG 1 T-DRAM helps implement a high-reliability single-cell memory device.

Reliability improvement of self-heating effect, hot-carrier injection, and on-current variation by electrical/thermal co-design

In order to achieve reliability improvement in metal–oxidesemiconductor field-effect transistor (MOSFET), the asymmetric MOSFET has been proposed and investigated. The lightly doped drain (LDD) region in asymmetric MOSFET acts as effective heat sink due to high thermal conductivity of LDD region, and self-heating effect (SHE) is consequently improved. In addition, it has been demonstrated that the proposed asymmetric MOSFET also has advantage of hot-carrier injection (HCI) and on-current variation (ΔION) due to its structure. In order to validate the proposed asymmetric MOSFET, technology computer-aided design (TCAD) simulation is conducted through Synopsys Sentaurus simulation tool. As a result, by utilizing the structure of asymmetric MOSFET, SHE is remarkably improved from 460 K to 392 K, and HCI is reduced by about 50 times, and ΔION is also simultaneously improved.