Dynamic Avalanche Limit and Current Filamentation Onset Limit in 4H-Silicon Carbide High-Voltage Diodes

Abstract

Dynamic avalanche (DA) phenomena and current filament (CF) formation are two extreme conditions observed in high-power devices, setting the maximum limit on turn-on/off current capability and di/dt in silicon (Si)-based bipolar devices. The properties of the silicon carbide (SiC) material enable devices with increased resilience for DA and CF compared with Si counterparts, and thus the safe-operating-area (SOA) limits may be extended. In this study, the limit of DA and CF in SiC-based semiconductor structures are investigated by numerical technology computer-aided design (TCAD) simulations, for different current levels, di/dt, and temperatures for high-voltage devices (e.g., 20-kV class). DA is first indicated for di/dt beyond 105 kA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> for current densities in the range of 50–1000 A/cm2, at 448 K. Similarly, stray-inductance-induced avalanche conditions are initiated above 33 kA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> , while CF is initiated for di/dt starting from 83 kA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> for current densities in the range of 8.3 kA/cm2. Moreover, the effects of the stray inductance in the main circuit loop are studied which may cause critical voltage transients during certain operating conditions. The outcome of the study may be useful to determine SOA limits and to be used as input for power electronic converter design and gate driver design for high-power electronic systems.