Technology Computer-aided Design Simulation Research Articles

Comprehensive Design and Analysis of Thin Film Sb2S3/CIGS Tandem Solar Cell: TCAD Simulation Approach

Abstract This research presents a design and analysis of a tandem solar cell, combining thin film wide bandgap Sb2S3 (1.72 eV) and narrow bandgap CIGS (1.15 eV) for the top and bottom sub-cells, respectively. The integration of all thin film layers enhances flexibility, rendering the tandem solar cell suitable for applications such as wearable electronics. To optimize the power conversion efficiency (PCE) of the tandem solar device, advanced technology computer-aided design (TCAD) simulation tools are employed to estimate loss mechanisms and fine-tune parameters for each layer. An experimentally validated optoelectronic model is introduced, calibrated and validated against fabricated reference solar cells for the individual top and bottom cells. The calibrated model is then utilized to propose optimization routines for the Sb2S3/CIGS tandem solar cell. The initial tandem cell exhibits a JSC of 15.72 mA/cm2 and a PCE of 15.36%. The efficiency drop in the tandem configuration is identified primarily in the top cell. A systematic optimization process for the top cell is initiated, exploring various configurations, including HTL-free and ETL-free setups. Moreover, an np homojunction structure for the top cell is proposed. Optimization routines are applied that involve determining optimal thickness and doping concentration of the n-layer, investigating the effect of p-layer doping concentration, and exploring the influence of the work function of the front contact. As a result, the tandem cell efficiency is significantly improved to 23.33% at the current matching point (CMP), with a JSC of 17.15 mA/cm2. The findings contribute to the advancement of thin-film tandem solar cell technology, showcasing its potential for efficient and flexible photovoltaic applications.

A design methodology for highly reliable operation for 2T0C DRAM application based on IGZO CAA FeFETs

Abstract In this paper, the memory characteristics of In-Ga-Zn-O (IGZO)-channel ferroelectric FETs (FeFETs) with stackable vertical Channel-All-Around (CAA) structure are investigated by technology computer-aided design (TCAD) simulation. The simulated IDS~VGS curves of IGZO FeFET exists a large on-off ratio of 107 and memory window, proving that ferroelectric hafnium oxide is satisfied for 2T0C transistor design. To solve the potential current sharing problem of 2T0C dynamic random access memory (DRAM) array, an advanced operation design methodology is proposed, which utilizes the bipolar polarization characteristics of ferroelectric hafnium oxide. This solution shows the remarkable current ratio between data “1” and data “0”, not only demonstrating the feasibility of IGZO-based FeFET on 2T0C DRAM memory cell, but also providing array design guideline for highly reliable 2T0C memory applications.

Modeling and Bulk Characterization of 4HSIC Radiation Detector in Sentaurus TCAD Simulation Environment

This paper gives an insight into the need for radiation detection and the most commonly flexible and efficient radiation detector. It also examines bulk characteristics of 4H-SiC semiconductor radiation detector with Ni and Ti as metals for the contact. Bulk characterization of the device, including: doping concentration, electrons and holes behaviors, space charge and current densities were carried out. The modeling is conducted using Sentaurus Technology Computer Aided Design (TCAD) to examine charge transport in bulk 4HSiC material. Data obtained were further analyzed through Sentaurus visual, sentaurus Techplot and Excel to clearly determine the characteristics of the device. It is observed that when the semiconductor and metal are in contact, the Fermi-level is established where the doping concentration varied with either magnitude of the doping concentration or nature of the dopant. Similarly, Schottky and ohmic contacts and temperature effect were observed from the device characteristics which demonstrate that, the detector can withstand a temperature from the range of 100K to 700K in no fluctuating state.

Study on the single-event burnout mechanism of p-GaN gate AlGaN/GaN HEMTs

In this work, the single-event burnout (SEB) mechanism of p-GaN gate AlGaN/GaN HEMTs has been studied systematically. The irradiation experiment was carried out based on Ta ions with high linear energy transfer of 75.4 MeV/(mg/cm2), a standard criterion for commercial space applications. It is clearly observed that both the drain current and gate current increase during the irradiation. With the increasing drain bias, the device burns out eventually. Technology computer-aided design simulation was used to explore the possible burnout mechanism. The local high electric field peak induced by the electron and hole redistribution was proposed to explain the permanent damage. When heavy ions impact the device, electron–hole pairs are formed. With the aid of a horizontal electric field across the channel, electrons and holes move toward the drain and gate, respectively. The accumulation of electrons and holes around the drain edge and gate edge induces the local high electric field, which is even higher than the intrinsic breakdown electric field of GaN and AlGaN. The scanning electron microscope results verified the proposed SEB mechanism. This research offers significant theoretical and experimental insights for evaluating the reliability of GaN power devices against high-energy single-event burnout in aerospace applications.

Enhanced Breakdown Voltage of AlGaN/GaN MISHEMT using GaN Buffer with Carbon-Doping on Silicon for Power Device

In recent years, Gallium Nitride (GaN)-based metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) have attracted interest in high-power and high-frequency applications. The breakdown mechanism in E-mode GaN MISHEMTs with carbon doping in the GaN buffer grown on a Silicon (Si) substrate (Sub) was investigated using technology computer-aided design simulations. Results showed that GaN MISHEMTs without Si Sub had a breakdown voltage (BV) of 600 V. However, after adding Si Sub to the GaN buffer layer, the electric field (EF) increased, creating a vertical breakdown through the total buffer thickness, therefore, BV was reduced to around 240 V. On the other hand, BV is increased to approximately >1100 V, and the Electric field is reduced after employing a carbon deep acceptor with the proper doping concentration in this device. The GaN MISHEMTs with Si Sub is presented as threshold voltage +1.5 V with transconductance of 700 mS/mm, which is an excellent result compared to GaN MISHEMTs without Si Sub. Eventually, the study device depicted higher BV performance compared to other C-doped GaN HEMT devices. This suggests that the designed GaN MISHEMTs device could effectively be used in power semiconductor devices with optimum performance.

Characteristics of β-(AlxGa1−x)2O3/Ga2O3 dual-metal gate modulation-doped field-effect transistors simulated by TCAD

β-(AlxGa1−x)2O3/Ga2O3 modulation-doped field-effect transistors (MODFETs) with a dual-metal gate (DMG) architecture are designed, and the electrical characteristics of the DMG device are investigated in comparison with the single-metal gate (SMG) device by the Technology Computer-Aided Design (TCAD) simulation. The results demonstrate that the DMG MODFETs possess a superior transconductance (gm), current gain cut-off frequency (fT), and power gain cut-off frequency (fMAX) than those of SMG transistors, which is attributed to the regulated channel electric field by a DMG structure. With a gate length of 0.1 μm, the peak values of fT/fMAX of the designed DMG MODFET are obtained as 48.6/50.6 GHz, respectively. Moreover, a comprehensive thermal analysis is conducted between the SMG and DMG devices under steady-state and transient conditions. The DMG MODFET exhibits a lower maximum temperature than the SMG counterpart due to the reduced channel electric field, each subjected to the same power dissipation. This finding underscores the potential of the β-(AlxGa1−x)2O3/Ga2O3 MODFET with the DMG architecture as a promising approach for high-power radio frequency operations.

Study of the mechanism of single event burnout in lateral depletion-mode Ga2O3 MOSFET devices via TCAD simulation

This study investigates the sensitive region and safe operation voltage of single-event burnout (SEB) in lateral depletion-mode Ga2O3 MOSFET devices via technology computer aided design simulation. Based on the distribution of the electric field, carrier concentration, and electron current density when SEB occurs, the radiation damage mechanism of SEB is proposed. The mechanism of SEB in Ga2O3 MOSFET was revealed to be the result of a unique structure without a PN junction within it, which possesses gate control ability and exerts a significant influence on the conduction of the depletion region.

Double-gate structure enabling remote Coulomb scattering-free transport in atomic-layer-deposited IGO thin-film transistors with HfO2 gate dielectric through insertion of SiO2 interlayer

In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μFE) of 65.1 ± 2.3 cm2V−1 s−1, subthreshold swing of 65 ± 1 mVdec−1, and threshold voltage (VTH) of 0.42 ± 0.05 V. Both the (μFE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μFE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible VTH shift of − 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of − 2 MVcm−1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects.

Analysis of Mechanical Stress on Fowler-Nordheim Tunneling for Program Operation in 3D NAND Flash Memory

This study investigated the relationship between mechanical stress and program efficiency in three-dimensional (3D) NAND flash memory devices. A stacked memory array transistor (SMArT) 3D NAND flash structure was modeled using a technology computer-aided design (TCAD) simulation. The mechanical stress distribution in the device depended on the deposition temperature (TD) of the constituent material. In particular, the TD of tungsten (TD,W) dominated the mechanical stress. The tensile stress on the polycrystalline silicon (poly-Si) channel increased as the TD,W decreased, and the compressive stress on the tunneling oxide (Tox) decreased. Consequently, the barrier height between Tox and poly-Si, and the effective electron mass decreased as the electric field in the Tox increased. These changes significantly increased the Fowler-Nordheim (FN) tunneling process and program efficiency, indicating the crucial performance of 3D NAND flash. Moreover, the mechanical stress caused by the differences in TD,W improved the program efficiency at a lower program voltage (VPGM). Therefore, a change in the mechanical stress based on decreasing TD,W improved the program efficiency through a higher FN tunneling process.

Two- and Three-Dimensional Recrystallization of Discrete Amorphous in C3H5-Molecular-Ion-Implanted Silicon Surface Analyzed by TCAD Simulation

Technology computer-aided design (TCAD) kinetic Monte Carlo simulations revealed the unique recrystallization processes of discrete amorphous regions connected to a buried amorphous layer in a C3H5-molecular-ion-implanted silicon (Si) substrate. The faithful simulation models show that the discrete amorphous regions are first recrystallized two-dimensionally in the lateral direction from both sides and separated from the buried amorphous layer. Then, the separated discrete amorphous regions are recrystallized three-dimensionally in the lateral and vertical directions from both sides and the bottom. We found that the first two-dimensional recrystallization of discrete amorphous regions is caused by the retardation of solid-phase epitaxial growth at the Si substrate surface and near the buried amorphous layer. We also found that the large (small) discrete amorphous regions require a long (short) two-dimensional recrystallization before separating from the buried amorphous layer. The transition point in the recrystallization dimension can be determined from the lateral recrystallization length and the equivalent radius of discrete amorphous regions.

A 3-D GaAs-based Hall sensor design with dual active layers structure

A fully integrated 3-D Hall magnetic sensor with dual active structure was proposed. Results by technology computer-aided design simulation show that the proposed sensor provides a doubled magnitude improvement in sensitivity of vertical magnetic field direction and maintains a good level sensing of horizontal magnetic field direction compared with the sensor with single active layer. The designed sensor was fabricated by wet etching process and a method of preparing Ohmic contacts on the "pseudo-sidewalls" is proposed. The measurements show that the non-linearity does not exceed 0.5% and a voltage sensitivity of up to 0.046 T−1, which matches the simulation results. The proposed sensor boasts a simplified structure that allows for fabrication using different layers only through a planar process, which makes it more conducive to the integration of devices and systems.

Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory

This paper presents an innovative approach to alleviate Z-interference in 3D NAND flash memory by proposing an optimized confined nitride trap layer structure. Z-interference poses a significant challenge in 3D NAND flash memory, especially with the reduction in cell spacing to accommodate an increased number of vertically stacked 3D NAND flash memories. While the confined nitride trap layer device designed for complete isolation of the trapping layer in three dimensions effectively reduces Z-interference, the results showed substantial variations based on the confined structure. To clarify this issue, we compared three distinct confined nitride trap layer structures and investigated their impact on Z-interference. Our findings indicate that the rectangle structure exhibited the most significant mitigation, implying that differences in the electric field applied to the poly silicon channel, which is influenced by the structure, and the increase in effective channel length are effective strategies for alleviating Z-interference. The proposed structure undergoes a comprehensive examination through technology computer-aided design (TCAD) simulations. Additionally, we introduce a practical process flow designed to minimize Z-interference.

Design and 3D TCAD simulation of a novel floating-electrode silicon pixel detector

A novel floating-electrode silicon pixel detector has been proposed. The novel configuration of the floating electrode in the silicon pixel detector reduces the size of the collecting cathode and decreases both the capacitance and leakage current of the detector compared to the conventional silicon pixel detector. For the design, we used a 200 × 200 µm2 detector as the model to analyze the impact of varying numbers of floating rings on the electrical performance [Wu et al., AIP Adv. 11(2), 025315 (2021)]. We used Technology Computer Aided Design simulation to compare and analyze the simulated electric field, potential, capacitance, and breakdown voltage of the detector. The results show that decreasing the gap-to-width ratio of the floating electrode, as well as increasing the quantity of floating rings, enhances the detector’s performance.

Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

AbstractIn the present work, we investigate the impact of structure dimensional parameters on the short channel effects which occurs especially below 20 nm regime particularly gate induced drain leakage (GIDL) current. Using technology computer aided design simulation (TCAD), we have examined the GIDL for SiGe as source/drain in NTJLFET. The structural dimensional parameters such as the nanotube thickness, core and outer gates thickness and gate electrode work function shows the significant impact on the band to band tunneling in lateral direction (L‐BTBT) which induced GIDL current. It is analyzed that increase in the nanotube thickness and physical oxide thickness increase the GIDL current, while increasing the gate electrode work function, core gate and outer gate thicknesses gives reduced GIDL current. The SiGe S/D NTJLFET produce a remarkable high ION/IOFF ratio ~ 1011. A compact model for GIDL current is also developed which shows the dependency of structure parameters on leakage current. The SiGe has been incorporated as source and drain in NTJLFET which creates the energy band discontinuity. Furthermore, SiGe S/D NTJLFET is fairly compared with the conventional NT JLFET and nanowire (NW) JLFET and shows an improved performance.

Simulation Research on High-Voltage β-Ga2O3 MOSFET Based on Floating Field Plate

The simulation model of a depletion-mode (D-mode) β-Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET) is constructed by Silvaco ATLAS technology computer-aided design (TCAD) simulation, which employs an epitaxial drift layer grown on a sapphire substrate. On this basis, the floating field plate (F-FP) structure based on the gate-pad-connected field plate (P-FP) is proposed to improve the breakdown characteristics of the device, which is easy to be prepared. The working principle of F-FP is investigated with the help of the device with one F-FP. Based on the principle that the number of floating field plates is increased on an optimized floating field plate structure. Subsequently, the devices with two and three floating field plates are simulated in turn, and the optimal structural parameters of the three F-FPs device are finally obtained, and the breakdown voltage is 3800 V at this time. In addition, it is found that the device breakdown voltage is increased by approximately 500–600 V for each additional floating field plate.

Two-temperature principle for evaluating electrothermal performance of GaN HEMTs

Self-heating effects in Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) can adversely impact both device reliability and electrical performance. Despite this, a holistic understanding of the relationship among heat transport mechanisms, device reliability, and degradation of electrical performance has yet to be established. This Letter presents an in-depth analysis of self-heating effects in GaN HEMTs using technology computer-aided design and phonon Monte Carlo simulations. We examine the differential behaviors of the maximum channel temperature (Tmax) and the equivalent channel temperature (Teq) in response to non-Fourier heat spreading processes, highlighting their respective dependencies on bias conditions and phonon ballistic effects. Our study reveals that Tmax, a crucial metric for device reliability, is highly sensitive to both heat source-related and cross-plane ballistic effects, especially in the saturation regime. In contrast, Teq, which correlates with drain current degradation, shows minimal bias dependence and is predominantly influenced by the cross-plane ballistic effect. These findings emphasize the importance of optimizing device designs to mitigate both Tmax and Teq, with a particular focus on thermal designs influenced by the heat source size. This work contributes to a deeper understanding of self-heating phenomena in GaN HEMTs and provides valuable insights for enhancing device performance and reliability.

Robust reverse bias safe operating area and improved electrical performance in 3300 V non-proportionally scaled insulated gate bipolar transistors

Robustness under high-temperature clamped inductive turn-off has been compared systematically among 3300 V scaled insulated gate bipolar transistors (IGBTs) with scaling factor k from 1 to 10 by technology computer-aided design simulations. Degradation of the reverse bias safe operating area (RBSOA) has been observed in proportionally scaled IGBTs, especially at a high turn-off current density. A non-proportional scaling method has been proven to be able to restore the robustness degradation with RBSOA close to the original k = 1 case. Moreover, the method for adjusting R pf (P-floating connecting resistor) adds more flexibility to device design and also improves the overall electrical performance of non-proportionally scaled IGBTs. The adjustment of R pf has been found to have a minimal effect on the RBSOA.

Prediction of JTE breakdown performance in SiC PiN diode radiation detectors using TCAD augmented machine learning

The design of Junction Termination Extension (JTE) is an important step for meeting the reliability requirement of SiC PiN diode radiation detectors. For early evaluation, Technology Computer Aided Design (TCAD) software is often used to simulate the electronic property of detectors with different JTE parameters. But it is time consuming, which need 1 h or even longer for one case. Here, a TCAD augmented Machine Learning (ML) method based on the fully connected Neural Network (NN) algorithm is proposed to predict the breakdown performance quickly with different parameters of Spatial Modulation (SM) JTE. Utilized ∼5000 datum generated by TCAD simulation, the ML model could be established and achieve good prediction of breakdown voltage and location within a few seconds. As a semi-supervised learning model, its prediction accuracy of breakdown location is higher than 89.4 % and the determination coefficient R2 of breakdown voltage could be up to 0.97 compared with TCAD simulations. Moreover, this model could give the relationship curve of breakdown voltages and doping concentration, which is useful to choose an ideal structure with a wide implantation dose window. Based on this ML prediction model, the design cycle of SiC PiN diode radiation detectors could be reduced significantly.

Tailoring Subthreshold Swing in A-IGZO Thin-Film Transistors for Amoled Displays: Impact of Conversion Mechanism on Peald Deposition Sequences.

Amorphous IGZO (a-IGZO) thin-film transistors (TFTs) are standard backplane electronics to power active-matrix organic light-emitting diode (AMOLED) televisions due to their high carrier mobility and negligible low leakage characteristics. Despite their advantages, limitations in color depth arise from a steep subthreshold swing (SS) (≤ 0.1 V/decade), necessitating costly external compensation for IGZO transistors. For mid-size mobile applications such as OLED tablets and notebooks, it is important to ensure controllable SS value (≥ 0.3 V/decade). In this study, a conversion mechanism during plasma-enhanced atomic layer deposition (PEALD) is proposed as a feasible route to control the SS. When a pulse of a diethylzinc (DEZn) precursor is exposed to the M2 O3 (M = In or Ga) surface layer, partial conversion of the underlying M2 O3 to ZnO is predicted on the basis of density function theory calculations. Notably, significant distinctions between In-Ga-Zn (Case I) and In-Zn-Ga (Case II) films are observed: Case II exhibits a lower growth rate and larger Ga/In ratio. Case II TFTs with a-IGZO (subcycle ratio of In:Ga:Zn = 3:1:1) show reasonable SS values (313mV decade-1 ) and high mobility (µFE ) of 29.3cm2 Vs-1 (Case I: 84mV decade-1 and 33.4cm2 Vs-1 ). The rationale for Case II's reasonable SS values is discussed, attributing it to the plausible formation of In-Zn defects, supported by technology computer-aided design (TCAD) simulations.

Advances in the TCAD modelling of non-irradiated and irradiated Low-Gain Avalanche Diode sensors

The recently developed Low-Gain Avalanche Diode (LGAD) technology has gained growing interest within the high-energy physics (HEP) community, thanks to its capability of internal signal amplification that improves the particle detection. Since the next generation of HEP experiments will require tracking detectors able to efficiently operate in environments where expected fluences will exceed 1 × 1017 1 MeV n eq/cm2, the design of radiation-resistant particle detectors becomes of utmost importance. To this purpose, Technology Computer-Aided Design (TCAD) simulations are a relevant part of the current detector R&D, not only to support the sensor design and optimization, but also for a better understanding and modelling of radiation damage. In this contribution, the recent advances in the TCAD modelling of non-irradiated and irradiated LGAD sensors are presented, whose validation relies on the agreement between the simulated and experimental data — in terms of current-voltage (I-V), capacitance-voltage (C-V), and gain-voltage (G-V) characteristics, coming from devices manufactured by Hamamatsu Photonics (HPK), and accounting for different irradiation levels and temperatures.