Technical Computer-aided Design Research Articles

Effect of hydrogen treatment on 4H-SiC Schottky barrier diodes

In this letter, 4H-SiC Schottky barrier diodes (SBDs) with Ti Schottky metal have been subjected to hydrogen treatment in a confined environment of 4% H2 and 96% N2 at 150 °C. The effect of hydrogen treatment on the SBDs electrical characteristics has been investigated by technical computer-aided design simulation (TCAD) and power device analyzer curve tracer. The change of electrical parameters of SBDs measured after hydrogen treatment is studied in detail, and the related degradation mechanism is discussed. It was found that hydrogen treatment affected both the interface region and bulk region of SiC SBDs. After hydrogen treatment, the Schottky barrier increases slightly, the ideal factor (n) decreases slightly, and the interfacial state density (D it) decreases. Hydrogen treatment resulted in a slight reduction in specific on-resistance (R on-sp), which was attributed to the diffusion of H in SBDs. Through TCAD simulation, it is determined that the diffusion of H in the body diode of SBDs is the main reason for the degradation of high forward current and high reverse voltage characteristics.

Source/Drain Extension Asymmetric Counter-doping for Suppressing Channel Leakage in Stacked Nanosheet Transistors

In the relentless pursuit of semiconductor device scaling, stacked silicon nanosheet gate-all-around field-effect transistors (NSFETs) are emerging as key candidates for sub-3nm technology nodes. However, the challenge of channel leakage in these devices is critical and necessitates innovative solutions. A novel SDE asymmetric counter-doping technique is proposed in this study. It investigates the impact of source/drain extension on device performance using different process schemes through three-dimensional technical computer-aided design (3D TCAD) simulations. The simulations demonstrate a comprehensive technically advantages for 25.2% / 16.65% reduction in the off-state leakage, 27.36% / 15.03% improvement in the on-off current ratio of N / P NSFETs, respectively. Furthermore, it shows more performance gain as the gate length scaling beyond 3nm technology nodes. The compatibility of the asymmetric counter-doping method with mainstream NSFET integration flows and its scalability to 10 nm gate lengths indicate that it is a promising approach to optimize NSFETs performance with little extra process cost.

Dependence of a Hydrogen Buffer Layer on the Properties of Top-Gate IGZO TFT.

In this paper, the effect of a buffer layer created using different hydrogen-containing ratios of reactive gas on the electrical properties of a top-gate In-Ga-Zn-O thin-film transistor was thoroughly investigated. The interface roughness between the buffer layer and active layer was characterized using atomic force microscopy and X-ray reflection. The results obtained using Fourier transform infrared spectroscopy show that the hydrogen content of the buffer layer increases with the increase in the hydrogen content of the reaction gas. With the increase in the hydrogen-containing materials in the reactive gas, field effect mobility and negative bias illumination stress stability improve nearly twofold. The reasons for these results are explained using technical computer-aided design simulations.

A high-performance terahertz detector based on a graded channel GaN high-electron-mobility transistor with a recessed gate

A novel recessed gate graded AlGaN high-electron-mobility transistor (RGGA HEMT) for high-sensitivity terahertz (THz) detectors is reported, which exhibits significant potential for high-sensitivity THz detectors, and consequently. The simulation results indicate the exceptional field-effect factor of the proposed RGGA HEMT, which is largely attributed to the three-dimensional electron gas generated by the graded AlGaN barrier layer and the subsequent enhancement of channel conductance. The responsivity and noise equivalent power reach 58mA/W and 43pW/Hz respectively at 227GHz by utilizing a technical computer-aided design platform. As compared to conventional structure GaN HEMT experimental data, the current responsivity is improved by 2.64 times, and the NEP is reduced by 43.4%. The unprecedented improvement in detection performance renders the RGGA HEMT a highly promising approach for future THz real-time single-pixel imaging applications at room temperature.

Study of High-Energy Proton Irradiation Effects in Top-Gate Graphene Field-Effect Transistors

In this article, the effects of high-energy proton irradiation on top-gate graphene field-effect transistors (GFETs) were investigated by using 20 MeV protons. The basic electrical parameters of the top-gate GFETs were measured before and after proton irradiation with a fluence of 1 × 1011 p/cm2 and 5 × 1011 p/cm2, respectively. Decreased saturation current, increased Dirac sheet resistance, and negative drift in the Dirac voltage in response to proton irradiation were observed. According to the transfer characteristic curves, it was found that the carrier mobility was reduced after proton irradiation. The analysis suggests that proton irradiation generates a large net positive charge in the gate oxide layer, which induces a negative drift in the Dirac voltage. Introducing defects and increased impurities at the gate oxide/graphene interface after proton irradiation resulted in enhanced Coulomb scattering and reduced mobility of the carriers, which in turn affects the Dirac sheet resistance and saturation current. After annealing at room temperature, the electrical characteristics of the devices were partially restored. The results of the technical computer-aided design (TCAD) simulation indicate that the reduction in carrier mobility is the main reason for the degradation of the electrical performance of the device. Monte Carlo simulations were conducted to determine the ionization and nonionization energy losses induced by proton incidence in top-gate GFET devices. The simulation data show that the ionization energy loss is the primary cause of the degradation of the electrical performance.

Analysis of Multiple Fin-type Vertical GaN Power Transistors based on Bulk GaN Substrates

In this study, the multiple fin-type vertical GaN power transistor based on the GaN-on-GaN were analyzed using the two-dimensional technical computer-aided design (2-D TCAD) simulations. In the field of the electric vehicle systems requiring a high operation voltage of 1,000 V or more, the power devices have a large device area because of the long distance between the gate region and the drain region. This problem can be addressed by using the fin-type vertical GaN power transistor, which can reduce the device area due to its vertical channel. For the high current performance, the multiple fin-type structure was required. Thus, we investigated characteristics depending on the number of fin (NSUBfin/SUB). By comparing the on-state drain currents (ISUBon/SUB), the breakdown voltages (BV), and the on-resistances (RSUBon/SUB) with different NSUBfin/SUB, this study provides an understanding of the electrical properties of the multiple fin-type vertical GaN power transistor affected by NSUBfin/SUB.

Novel Channel-First Fishbone FETs With Symmetrical Threshold Voltages and Balanced Driving Currents Using Single Work Function Metal Process

In this article, one feasible fabrication approach for novel fishbone FETs using the channel-first and single work function metal (sWFM) processes is proposed and investigated by 3-D technical computer-aided design (TCAD) simulations. Through a small modification on the fabrication process of general gate-all-around (GAA) nanosheet FETs (NSFETs), the special fishbone-like channel composed of vertically stacked Si NSs and sandwiched SiGe nano-fins is experimentally demonstrated by the channel-first process. The simulated electrical characteristics show that the width of the nano-fins should be within 5 nm for a better gate control. Unlike traditional NSFETs, symmetrical threshold voltages ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}\text{s}$ </tex-math></inline-formula> ) for n-type and p-type fishbone FETs can be achieved by using a sWFM, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text {th}}$ </tex-math></inline-formula> is optimized by 99.26% compared with that of NSFETs. Meanwhile, it is also found that the SiGe nano-fins contribute more driving current for p-type devices. Therefore, the proposed fishbone FETs with sWFM not only exhibit significantly enhanced driving current but also provide good balance between the performances of n-type and p-type fishbone FETs with a little extra process cost.

Cold Carrier Injection Mechanism for Gate Oxide Integrity of High Voltage NDMOS

This article studies a reliability mechanism for field-plate-assisted reduced surface field (RESURF) effect 225-V NDMOS devices based on anode hole oxide injection for carriers that are in thermal equilibrium with the surrounding lattice. The injection mechanism is facilitated by a unique combination of layout and application biases that result in electric field vectors pulling low-energy minority hole carriers into oxide traps that overlap the drain potential. The effect of this positive charge trapping along the field oxide is to inhibit the RESURF mechanism, while also weakening the gate oxide where it overlaps the drain that ultimately results in a rupture. To quantify the process, a new accelerated aging technique is described that uses the parasitic n-p-n bipolar parallel of the nMOS channel to significantly increase the number of holes while still maintaining the MOS application voltages needed to enable the mechanism. This provides a cost-effective way to accurately accelerate this reliability mechanism with significantly smaller lead times relative to using higher biases and temperatures. This technique is then used with technical computer-aided design (TCAD) analysis to determine the impact of different manufacturing variables, where process controls are introduced for targeted manufacturing limits that can eliminate this mechanism from occurring.

LoGHeD: an effective approach for negative differential resistance effect suppression in negative-capacitance transistors

A negative capacitance transistor with fully depleted silicon-on-insulator (FDSOI) technology (NC-FDSOI) is one of the promising candidates for next-generation low-power devices. However, it suffers from the inherent negative differential resistance (NDR) effect, which is very detrimental to device and circuit designs. Aiming at overcoming this shortcoming, this paper proposes for the first time to use local Gaussian heavy doping technology (LoGHeD) in the channel near the drain side to suppress the NDR effect in the NC-FDSOI. The technical computer-aided design simulation results have validated that the output conductance (G DS) with LoGHeD, which is used to measure the NDR effect, increases compared to the conventional NC-FDSOI counterpart and approaches zero. With the increase in doping concentration, the inhibitory capability of the NDR effect shows a monotonously increasing trend. In addition, the proposed approach maintains and even enhances performances of the NC-FDSOI transistor regarding the electrical parameters, such as threshold voltage (V TH), sub-threshold swing, switching current ratio (I ON/I OFF), and drain-induced barrier lowering.

Electrical Performances of GaN-based Vertical Trench MOSFETs with Cylindrical and Hexagonal Structure

In this paper, we designed and analyzed the electrical performances of gallium-nitride (GaN)-based vertical trench metal-oxide-semiconductor field-effect-transistors (MOSFETs) using three-dimensional technical computer-aided design (3-D TCAD) simulation. The cylindrical device is generally considered as superior device than the polygonal devices because it has better gate controllability. In the case of GaN-based vertical devices, however, the cylindrical device performs inferiorly to the hexagonal device in terms of crystal directions for the GaN sidewall plane such as m-plane (1-100), a-plane (11-20), and c-plane (0001). The simulation results provide an understanding and design guidelines for which electrical properties of trench FETs are affected by cross-section shape.

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices.

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

The Study of the Single Event Effect in AlGaN/GaN HEMT Based on a Cascode Structure

An attractive candidate for space and aeronautic applications is the high-power and miniaturizing electric propulsion technology device, the gallium nitride high electron mobility transistor (GaN HEMT), which is representative of wide bandgap power electronic devices. The cascode AlGaN/GaN HEMT is a common structure typically composed of a high-voltage depletion-mode AlGaN/GaN HEMT and low-voltage enhancement-mode silicon (Si) MOSFET connected by a cascode structure to realize its enhancement mode. It is well known that low-voltage Si MOSFET is insensitive to single event burnout (SEB). Therefore, this paper mainly focuses on the single event effects of the cascode AlGaN/GaN HEMT using technical computer-aided design (TCAD) simulation and heavy-ion experiments. The influences of heavy-ion energy, track length, and track position on the single event effects for the depletion-mode AlGaN/GaN HEMT were studied using TCAD simulation. The results showed that a leakage channel between the gate electrode and drain electrode in depletion-mode AlGaN/GaN HEMT was formed after heavy-ion striking. The enhancement of the ionization mechanism at the edge of the gate might be an important factor for the leakage channel. To further study the SEB effect in AlGaN/GaN HEMT, the heavy-ion test of a cascode AlGaN/GaN HEMT was carried out. SEB was observed in the heavy-ion irradiation experiment and the leakage channel was found between the gate and drain region in the depletion-mode AlGaN/GaN HEMT. The heavy-ion irradiation experimental results proved reasonable for the SEB simulation for AlGaN/GaN HEMT with a cascode structure.

Designing ESD Protection Devices for Ultrafast Overvoltage Events

This article provides an understanding of the transient voltage overshoot physics observed with electro-static discharge (ESD) n-type, p-type, and n-type diffusions (NPN) bipolar devices through the use of calibrated technical computer-aided design (TCAD) with measured silicon results. This analysis graphically steps through each stage of the measured transient electrical response, to explain the inertia that limits the speed of the NPN ESD cell, and then uses this knowledge to provide a fully characterized silicon solution for ultrafast ESD events to achieve an 8-kV IEC61000-4-4 rating. This solution is developed by exploring five different integrated designs that are constructed on an 80-V bipolar and complimentary double-diffused metal-oxide semiconductor (BiCDMOS) process platform to protect against a product level 125-V voltage overshoot gate oxide ruptures as measured with a 0.6-ns rise time transmission line pulse (TLP). The fully characterized electrical results for each test overshoot structure with a fixed layout area of $200\,\,\mu \text{m}\,\,\times200\,\,\mu \text{m}$ , are in parallel to NPN ESD cells arranged with two in series and two in parallel ( $200\,\,\mu \text{m}\,\,\times 80\,\,\mu \text{m}$ ) and compared in terms of the current-carrying capability before the gate oxide rupture voltage of 125 V is reached. The results show that a diode engineered with a vertical breakdown achieves an ESD strength of 9.7 A before the overshoot voltage reaches the target of 125-V, resulting in a net 0.17 mA $\mu \text{m}^{-{2}}$ . The combined use of this vertical diode structure in parallel to the NPN ESD cell translates into a 7-A improvement in the strength of a conventional NPN for ultrafast timescales, which achieves the 8-kV International Electrotechnical Commission (IEC) ESD performance for this case study.

Reverse-Bias Stress-Induced Electrical Parameters Instability in 4H-SiC JBS Diodes Terminated Nonequidistance FLRs

In this article, the breakdown voltage ( ${V}_{\text {BR}}$ ) shift of 4H-SiC Junction Barrier Schottky (JBS) diodes terminated by optimum nonequidistant field limiting rings (FLRs) subject to reverse-bias stress (RBS) has been investigated, and the corresponding mechanisms are studied in-depth. It can be observed that ${V}_{\text {BR}}$ gradually increases with increasing stress time, but there is no obvious shift of the forward voltage ( ${V}_{F}$ ). The increment in the magnitude of ${V}_{\text {BR}}$ induced by RBS testing is shown to depend strongly on the degree of applied reverse-bias voltage. The physical mechanism of ${V}_{\text {BR}}$ shift has been investigated and explained by means of numerical technical computer-aided design (T-CAD) simulations. Our analysis shows that the hole injection and trapping into SiO2 at the FLR terminal area are identified to be the main cause, resulting in the increase of ${V}_{\text {BR}}$ . Besides, a simple model is proposed to explain the behavior of ${V}_{\text {BR}}$ instability.

Impact of High-Temperature Storage Stressing (HTSS) on Degradation of High-Voltage 4H-SiC Junction Barrier Schottky Diodes

High-temperature storage stressing (HTSS) experiments were carried out on high-voltage 4H-SiC junction barrier Schottky (JBS) diodes. The effects of the high-temperature (up to 275 °C) storage under air environment on thermal stability of the 4H-SiC JBS are investigated. The electrical parameter shifts for tested diodes after the HTSS were investigated in detail, and related degradation mechanisms have been discussed. It is found that HTSS has no effect on the Schottky barrier height, the ideality factor ( n ), and specific on-resistance ( $R_{{\text{on-sp}}}$ ). However, it was interesting that the breakdown voltage ( $V_{{\text{BR}}}$ ) of the devices was decreased first and then increased as the storage time increased. With the analysis of the SiO2/4H-SiC interface characteristics using metal-oxide-semiconductor structure fabricated simultaneously with the investigated 4H-SiC JBS on the same wafer and technical computer-aided design (T-CAD) simulations, trapped-electrons and holes located at the interface of SiO2/4H-SiC on termination region are identified to be the basic reason causing the degradation of reverse characteristics in the devices.

Design guidelines for nanoscale vacuum field emission transistors

Nanoscale vacuum channel field emission transistors (VFETs) with different gate-structures, channel lengths, and emitter tip radii are comprehensively studied using technical computer-aided design simulation. With a multigate configuration, the operating gate voltage decreases and the transfer characteristics improve due to excellent gate controllability. The gate-all-around (GAA) VFET with short channel length and thin channel to gate distance would be most suitable for low power consumption and less sensitivity to device fluctuation. In order to further understand the impact of physical gate length on the on-current (Ion) and the gate leakage current in VFETs, full- and half-gate devices are compared. With shorter channel length and thinner channel to gate distance, the tunneling energy band becomes sensitive to the gate field, resulting in a more severe Ion fluctuation. The half-gate structure can mitigate the gate leakage current without sacrificing the on-current because the leakage current near the collector tip can be reduced in comparison to the full-gate structure. The GAA VFET also shows superior cut-off frequency performance resulting from high transconductance, compared with the single- and double-gate VFETs.

Repetitive-Avalanche-Induced Electrical Parameters Shift for 4H-SiC Junction Barrier Schottky Diode

The electrical parameters shift of 4H-SiC junction barrier Schottky diode under the repetitive avalanche current stress has been experimentally investigated. Using technical computer-aided design simulation and high resolution transmission electron microscopy analysis at atomic scale, it has been demonstrated that the forward voltage drop of the device has no variation during the stress due to the intactness of active area. However, the reverse breakdown voltage is gradually increased with the stress time, which results from hot electron injection and trapping into the SiO2 dielectric at the outer edge of p-type junction termination.

Extraction of Surface Recombination Velocity at Highly Doped Silicon Surfaces Using Electron-Beam-Induced Current

In this paper, we demonstrate that the surface recombination velocity of electrons S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n0</sub> at highly p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -doped silicon surfaces can be quantified using the electron-beam-induced current (EBIC) technique. First, the 3-D electron-beam sample interaction is simulated using CASINO Monte-Carlo software in order to generate the 3-D carrier generation profile. Subsequently, this carrier generation profile is used in Sentaurus Technical Computer-Aided Design device modeling, and the EBIC response is simulated as a function of S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n0</sub> . The simulation results show a near-perfect match with the EBIC measurements obtained on a passivated and depassivated p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -emitter of n-type silicon wafer solar cells. In addition, localized Sn0 extraction on an area of 30 × 30 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is presented, clearly illustrating the advantage of EBIC as an electron-beam-based characterization technique compared with optical techniques.

Working 225 V Over-Voltage Protection Cell With Tunable Trigger and Holding Voltages for Latch-Up Immunity

This paper describes the challenges encountered and solutions found to be the problem of developing over-voltage protection for 225 V circuit applications with measured tunable trigger voltages of 100-300 V, measured tunable holding voltages for latch-up immunity of 50-240 V, and corresponding strengths of 8.0-2.4 A Transmission Line Pulse (TLP). The device is engineered using technical computer-aided design and the performance is measured with dc characterization, unpowered TLP, powered and unpowered Electrostatic Discharge (ESD), as well as a 225 V product placement with a 1500-h High Temperature Operating Life lifetime reliability monitor. The final cell enables both 225 V powered and unpowered protection from high voltage switching transients and ESD events.

Advanced Modelling of Silicon Wafer Solar Cells

Modelling of solar cells today is general practice in research and widely-used in industry. Established modelling software is typically limited to one dimension and/or to small scales. Additionally, novel effects, like, e.g., the use of diffractive structures or luminescent materials, are not established. In this paper we discuss how the combination of different modelling techniques can be used to overcome these limitations. In this context two examples are presented. The first example concerns the combination of the open source simulation software PC1D with circuit modelling to investigate the effect of local shunts on the global characteristics of a silicon wafer solar cell. For the investigated example (4.5 cm2 cell area) we find that a local point shunt reduces the solar cell efficiency by 4% relative. The second example concerns the modelling of diffractive gratings for thin silicon wafer solar cells. For this purpose, we use the rigorous coupled wave analysis to simulate Sentaurus technical computer-aided design (TCAD) is combined with the rigorous coupled wave analysis, a method to solve Maxwell's equations for periodic structures. Here we show that a grating can be used to improve the absorption in a thin silicon wafer solar cell considerably.