TCAD Modeling Research Articles

Design of Superlattice Ferroelectric-Metal Field-effect Transistor for triple-level cell 3D NAND flash

Superlattice ferroelectric-metal field-effect transistor (SL-FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for triple-level cell (TLC) operations. The SL-FeMFET shows a novel approach for designing the gate-stack using a superlattice of ferroelectric/dielectric/ferroelectric for achieving large memory window ∼3.48 V with program/erase voltage ±7 V for 3D NAND architecture. By TCAD modeling, we demonstrate TLC operation of SL-FeMFET with improving memory window and alleviating variability caused by floating metal layer in FeMFET structure. In addition, as the vertical gate stack increases from 256-layer to 512-layer, the read-out current with worst cases in seven read operations for TLC sensing are examined using page buffer circuit for sensing operation. The simulation results suggest that SL-FeMFET based 3D NAND architecture can operate 512-layer with sufficient sense margin for TLC operation.

On the TCAD Modeling of Non-Permanent Gate Current Increase during Short-Circuit Test in SiC MOSFETs

Under short-circuit (SC) testing SiC MOSFETs exhibit an exceptional increase of gate current (100’s mA) which is not observed in their Si counterparts. Electro-thermal TCAD simulations are capable to accurately mimic all the details of measured gate current waveforms (iG) by capturing multiple physical mechanisms. One of these mechanisms is the thermionic or Schottky emission effect occurring at extreme temperatures (>1300K) for relatively thick gate oxides (>40nm). For the first time, it is proven that TCAD tunneling models, recommended for very thin oxides (<3nm), are suitable to reproduce the thermionic effect and predict iG in SiC MOSFETs under SC test.

Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level

Interface traps play a significant role in shaping the performance and reliability of semiconductor devices, particularly in advanced technologies such as Negative Capacitance based FinFET and Nanosheet (NS) FET. Hence, for the first time, using well calibrated TCAD models, we benchmark and explore into the analysis of interface traps in NC-FinFET and NC-NSFET devices at the sub-3 nm technology node, focusing on their effects on digital, analog/RF performance parameters. The investigation is mainly focussed on: (a) Positioning of acceptor (EV + 1 - EV-0.4) and donor (EC + 0.2 - EC-1.5) trap locations in the energy band (b) variation in acceptor and donor interface trap concentration (c) design of Common Source (CS) amplifier for analog integrated circuits. In addition, we explored a design space to achieve optimal capacitance matching, targeting the NC effect for an optimized device design. Our findings showed a significant improvement in ION/IOFF ratio by ~9× for NC-NSFET when compared to NC-FinFET with change in acceptor trap locations. The NC-FinFETs demonstrated a resilient intrinsic gain (AV) profile, making them suitable for high-speed amplifiers. Varying donor trap locations had minimal impact on NC-NSFET but slightly affected NC-FinFET's intrinsic gain profile. Moreover, increasing acceptor trap concentration improved digital performance, with NC-NSFET outperforming NC-FinFET and the analog/RF performance favored lower trap concentrations. In addition, NC-FinFETs were more resilient to increased donor traps concentration than NC-NSFETs. Further, the CS amplifier-based NC acceptor devices offered effective amplification and power-saving features, making them ideal for IoT and biomedical applications reliant on battery voltages.

Efficient Modeling of Single Event Transient Effect with Limited Peak Current: Implications for Logic Circuits.

The problem that the conventional double-exponential transient current model (DE model) can overdrive the circuit, which leads to the overestimation of the soft error rate of the logic cell, is solved. Our work uses a new and accurate model for predicting the soft error rate that brings the soft error rate closer to the actual. The piecewise double-exponential transient current model (PDE model) is chosen, and the accuracy of the model is reflected using the Layout Awareness Single Event Multi Transients Soft Error Rate Calculation tool (LA-SEMT-SER tool). The model can characterize transient current pulses piecewise and limit the peak current magnitude to not exceed the conduction current. TCAD models are constructed from 28 nm process library and cell layouts. The transfer characteristic curves of devices are calibrated, and functional timing verification is performed to ensure the accuracy of the TCAD model. The experimental results show that the PDE model is not only more consistent with TCAD simulation than the DE model in modeling the single event transient currents of the device, but also that the SER calculated by the LA-SEMT-SER tool based on the PDE model has a smaller error than the SER calculated by the LA-SEMT-SER tool based on the DE model.

A Physical TCAD Mobility Model of Amorphous In-Ga-Zn-O (a-IGZO) Devices with Spatially Varying Mobility Edges, Band-Tails, and Enhanced Low-Temperature Convergence.

Amorphous indium gallium zinc oxide (a-IGZO) is becoming an increasingly important technological material. Transport in this material is conceptualized as the heavy disorder of the material causing a conduction or mobility band-edge that randomly varies and undulates in space across the entire system. Thus, transport is envisioned as being dominated by percolation physics as carriers traverse this varying band-edge landscape of "hills" and "valleys". It is then something of a missed opportunity to model such a system using only a compact approach-despite this being the primary focus of the existing literature-as such a system can easily be faithfully reproduced as a true microscopic TCAD model with a real physically varying potential. Thus, in this work, we develop such a "microscopic" TCAD model of a-IGZO and detail a number of key aspects of its implementation. We then demonstrate that it can accurately reproduce experimental results and consider the issue of the addition of non-conducting band-tail states in a numerically efficient manner. Finally, two short studies of 3D effects are undertaken to illustrate the utility of the model: specifically, the cases of variation effects as a function of device size and as a function of surface roughness scattering.

Optimization of all-polymer/Sb2Se3 tandem solar cells for enhanced efficiency: a comprehensive TCAD modeling approach

Abstract This paper introduces a novel tandem configuration, utilizing an all-thin film all-polymer solar cell (all-PSC) with a wide bandgap of 1.76 eV for the front cell and Sb2Se3 with a narrow bandgap of 1.2 eV for the bottom cell. The design of this tandem is performed by comprehensive optoelectronic TCAD tools, essential for optimizing parameters across multiple layers to reach maximum power conversion efficiency (PCE). Experimental validation of models is conducted through calibration and validation against fabricated reference all-polymer and Sb2Se3 solar cells, yielding calibrated PCEs of approximately 10.1% and 10.5%, respectively. Subsequently, validated simulation models for both top and rear cells are utilized to design a 2-T all-polymer/Sb2Se3 tandem cell, which initially achieves a PCE of 10.91%. Through systematic optimization steps, including interface engineering and homojunction structure design, a remarkable PCE of 24.24% is achieved at the current matching point, showcasing the potential of our proposed tandem solar cell design. This study represents a significant advancement in the field of thin-film tandem solar cells, offering promising avenues for efficient and cost-effective photovoltaic technologies, particularly in applications requiring flexibility.

Numerical Simulation, Electrostatic and Physical Compact Modeling of C8-BTBT-C8 Organic Thin Film Transistor

This paper presents numerical simulation and compact modeling of 2,7-Dioctyl {1} benzothieno {3,2-b}{1} benzothiophene (C8-BTBT-C8) organic semiconductor-based TFT. It shows the entire modeling process flow of this organic semiconductor (OSC) and tests the device realization using a ring oscillator. The paper comprises OSC characterisation, band-gap modeling, electrostatic modeling, and capacitance modeling. The TCAD model consists of the Hopping and Pool Frenkel premise and characterizes the Density of State (DOS) for traps in deep and tail states. The findings from this research provide valuable information for improving OTFT models, enhancing their predictive accuracy, and advancing the understanding of organic semiconductor device behavior. The electrostatics demonstrate device structure dependency

Characterization and TCAD Modeling of the Lateral Space Charge Accumulation in Epoxy Molding Compound in Packaged HV-ICs

Characterization and TCAD Modeling of the Lateral Space Charge Accumulation in Epoxy Molding Compound in Packaged HV-ICs

Unveiling the reliability of negative capacitance FinFET with confrontation of different HfO2-ferroelectric dopants

The CMOS compatibility of Negative Capacitance (NC) FETs has been enhanced tremendously after introducing a thin film-doped HfO2 as a ferroelectric (FE) layer. For a given FE layer, the NC property is governed by specific HfO2 dopants (e.g., La, Zr, Al, Sr, Gd, Y, and Si). Thus, the TCAD simulation considerably depends on the dopant-specific Landau parameters (αx,βx,γx,ρx,gx), and its solidity needs proper attention. Further, the reliability of the NC devices is severely affected by process variations, i.e., interface trap charges, work function variation, random dopant fluctuation, and ambient temperature (external), which modulates the device threshold voltage (Vth); in turn, the device aging. In this paper, using well-calibrated TCAD models, we investigated reliability for the different dopant-specific NC-FinFET, in terms of Vth, ON current (ION), and OFF current (IOFF) modulation induced by: (i) the interface trap variability (ITV) considering the different trap concentration and energy location; (ii) the work function variability (WFV) considering different metal grain sizes (Gr); (iii) the random dopant fluctuations (RDF); and (iv) the ambient temperature. In this way, the device aging is calculated by inspecting Vth shift by ±50mV. These investigations pave the path for realizing a reliable NC-FinFET design.

Analysis of the behavior of TCAD and SPICE diode models in ESD protection circuits

To protect the interfaces of high-speed ICs from ESD, it is necessary to develop and optimize specialized protection circuit designs to minimize parasitic capacitance. The classic widely used designs based on ggMOS and SCR have too large parasitic capacitance, which degrades the parameters of the interface pins of the ICs. It is necessary to develop and optimize other ESD protection designs. One of the possible promising options is optimized diode protection. In this paper, an analysis of the effect of the design of a diode protection on its electrical characteristics is carried out. An analysis of the possibility of modeling protection using SPICE models was also performed and an assessment of the need to use TCAD simulation was carried out. Based on a comparison of the results of SPICE and TCAD simulations, it is shown that widely used SPICE diode models not optimal for designing and optimizing diode ESD protection. For this task, it is necessary to use TCAD simulation, taking into account the self-heating of the structure and the dynamics of the propagation of the thermal front. The results of this work are used for the development of ESD protection for interfaces of high–speed microcontrollers, DACs/ADCs, and transceivers.

A proof of concept for reliability aware analysis of junctionless negative capacitance FinFET-based hydrogen sensor

This work demonstrates the reliability-aware analysis of the Junctionless negative capacitance (NC) FinFET employed as a hydrogen (H2) gas sensor. Gate stacking of the ferroelectric (FE) layer induces internal voltage amplification owing to the NC property, thus, improving the sensitivity of the baseline junctionless FinFET. A well-calibrated TCAD model is used to investigate the sensing characteristics of the proposed FinFET-based H2 sensor by employing the palladium (Pd) metallic gate as a sensing element. The mechanism involves the transduction of H2 gas molecules over the metal gate; due to the diffusion process, some atomic hydrogen diffuses into the metal. The H2 gas absorption at the metal surface causes a dipole layer formation at the gate and oxide interface, which changes the metal gate work function. As a result, this change in the work function can be used as a sensing parameter of the proposed gas sensor. Further, the threshold voltage and other electrical characteristics, such as output conductance, transconductance, and drain current are examined for sensitivity analysis for both NC and without NC JL FinFET at different pressure ranges, keeping the temperature constant (i.e. 300 K). The device variation, i.e. Fin thickness, Fin height, doping and thickness of HfO2 ferroelectric layer, etc, on sensor sensitivity has been evaluated through extensive simulation. This paper also presents a detailed investigation of the sensor’s reliability in terms of work function variation, random dopant fluctuation, trap charges, and device aging, i.e. end of a lifetime. At last, the acquired results are compared with earlier reported data, which justifies the profound significance of the proposed junctionless negative capacitance FinFET-based H2 gas sensor.

A machine learning approach to TCAD model calibration for MOSFET

A machine learning approach to TCAD model calibration for MOSFET

Analysis of the transient dose rate effect on clock resources of JXCV5SX95T FPGA

This paper qualitatively investigates the transient dose rate effect (TDRE) on clock resources of the JXCV5SX95T FPGA, including DLL (Delay Locked Loop), PLL (Phase Locked Loop), and GCB (General Clock Buffer). Our previous experimental results showed that the sensitivity of different clock resources in the JXCV5SX95T FPGA presents prominent discrepancies. In particular, all input/outputs (IOs) present a simultaneous glitch during irradiations. And, the DLL and PLL would appear special short interrupt failures in some cases. However, the experimental results lack a mechanism analysis. In order to investigate the intrinsic mechanisms and in particular to compare the sensitivity differences between the PLL and DLL circuits, corresponding TCAD and SPICE simulations are performed. Both relevant DLL and PLL circuits are established in the SPICE simulator. The radiation-induced photocurrents are calculated by TCAD, and introduced into SPICE simulations. First, with an ideal power supply, the radiation performances of the DLL and PLL are simulated, and the influence of two factors are analyzed, including the substrate size of the TCAD model and the charge pump type of the DLL and PLL. Second, typical non-ideal power supply and IO models are used in the simulations. Simulation results indicate that the short interrupt of the PLL and DLL in experiments should result from the relevant power regulators in the FPGA. Last, piecewise linear voltage sources are applied to simulate the noise on the power supply in experiments, and their influence on the PLL, DLL, IOs are analyzed. Simulation results show that the simultaneous glitch in experiments may be mainly from the power supply noise, and the radiation effect of IOs would also contribute to this failure to some degree.

Characterization on the thermal field inside IGBT cells during switching based on TCAD modeling and Thermoreflectance imaging

—Temperature characterization of power semiconductors is a hot topic in power electronics. Nevertheless, the transient temperature field inside an IGBT cell is highly difficult to measure. In this study, we presented a method combining metallographic technology and Thermoreflectance Imaging (TRI) to measure the temperature distribution inside IGBT cells during switching. First, the IGBT module was prepared to achieve a well longitudinal section and its electrical characteristics were verified. Subsequently, the double-pulse test was performed on the IGBT sample and the temperature distributions along the ground section were measured through TRI. The result indicates that the temperature along the cross-section can be observed through TRI. The experimental results are confirmed to be consistent with the TCAD simulations on electro-thermal behavior. The proposed method for the first time achieves the direct temperature measurement inside the cells of power devices on a micro-nano temporal-spatial scale, and it can serve as an effective tool for analysis like temperature evaluation, aging analysis and TCAD modeling.

Low-Voltage Logic Gates based on Vertical GAA Nanotransistors

The issues of numerical simulation of low-voltage logic gates based on silicon vertical surrounding gate CMOS nanotransistors with a conical working area circuits are discussed. Using the TCAD instrument process modeling program, numerical studies of conical prototypes have been performed. The electrophysical characteristics in the control voltage range from 0 to 0.6 V are characterized by a higher transistor current, a maximum Ion/Ioff current ratio, a low leakage current and a slope of the subthreshold characteristic close to the theoretical aisle. 3D TCAD models of three basic logic gates on vertically arranged transistors of n-and p-types have been developed for an optimized ratio of the diameters of the working area of 8.4/10 nm and the length of the working area of 22 nm. Their electro-physical characteristics are numerically investigated at control voltages of 0.6 V and a frequency of 20 GHz. The gate models demonstrate picosecond delays and low power consumption. The promising characteristics of the proposed transistors and valves based on them, such as a high degree of integration, high performance and low cost, open the way to the development of 3D integrated circuits of the next generation.

Gate leakage modeling in lateral β -Ga2O3 MOSFETs with Al2O3 gate dielectric

We present a detailed model of the static and dynamic gate leakage current in lateral β-Ga2O3 MOSFETs with an Al2O3 gate insulator, covering a wide temperature range. We demonstrate that (i) in the DC regime, current originates from Poole–Frenkel conduction (PFC) in forward bias at high-temperature, while (ii) at low temperature the conduction is dominated by Fowler–Nordheim tunneling. Furthermore, (iii) we modeled the gate current transient during a constant gate stress as effect of electron trapping in deep levels located in the oxide that inhibits the PF conduction mechanism. This hypothesis was supported by a TCAD model that accurately reproduces the experimental results.

Physics-Integrated Machine Learning for Efficient Design and Optimization of a Nanoscale Carbon Nanotube Field-Effect Transistor

We propose an efficient framework for optimizing the design of Carbon Nanotube Field-Effect Transistor (CNTFET) through the integration of device physics, machine learning (ML), and multi-objective optimization (MOO). Firstly, we leverage the calibrated TCAD model based on experimental data to dissect the physical mechanisms of CNTFET, gaining insights into its operational principles and unique physical properties. This model also serves as a foundation, enabling multi-scale performance evaluations essential for dataset construction. In the ML phase, a chain structure of Support Vector Regression (SVR Chain) guided by a comprehensive statistical analysis of the design metrics is utilized to predict the design metrics. The surrogate model based on the SVR Chain achieves an average mean absolute percentage error (MAPE) of 1.59% across all design metrics without overfitting, even with limited data. The established ML model exhibits its competence in rapidly producing a global response surface for multi-scale CNTFET. Remarkably, an anomalous equivalent oxide thickness (EOT) and ON-state current (I on ) relationship is observed in CNTFET behavior due to extreme gate length scaling in long channel devices. This intriguing observation is further elucidated through a physics-based explanation. We further compare shallow and deep learning-based TCAD digital twins for model selection guidance. Using the Non-Dominated Sorted Genetic Algorithm-II (NSGA-II) in MOO, we harmonize metrics at both device and circuit levels, significantly reducing the design space. The closed-loop framework expedites the early-stage development of advanced transistors, overcoming the challenges posed by limited data.

Investigation of Analog/RF and linearity performance with self-heating effect in nanosheet FET

In vertically stacked gate-all-around Nanosheet FET (NSFET), the channels/sheets are wrapped by a low thermal conductivity material, which hinders the active heat flow path and, thus, raises reliability concerns. Therefore, the role of temperature, i.e., ambient condition and self-heating effect (SHE), become prime objectives that must be adequately addressed. In this work, through extensive TCAD simulations, we analyzed the DC/Analog/RF/Linearity characteristics of an NSFET, considering the cumulative effect of ambient temperature and SHE. Using well-calibrated TCAD models, we investigated: (i) the variation in device characteristics with and without considering SHE; (ii) the impact of SHE and ambient temperature on Analog/RF and Linearity characteristics using well-defined figure-of-merits (FoMs); (iii) the device optimization, i.e., the significance of the varying number of sheets (Nsheet) with considering SHE for optimal performance; (iv) the impact of varying temperature over the voltage gain of an NSFET-based common source (CS) amplifier considering SHE. The temperature variation (including SHE) significantly affects the ON current (e.g., reduced by 9.4%), resulting in the modulation in transconductance (gm). Therefore, the designed CS amplifier's gain is also altered by temperature variation (e.g., ranging from 250 K to 400 K). Hence, the proposed analysis is worth exploring to acquire the design guidelines for optimal and reliable DC/Analog/RF/Linearity characteristics of a Nanosheet transistor under various temperature conditions.

Single event response of ferroelectric spacer engineered SOI FinFET at 14 nm technology node

The impact of spacer on the single event response of SOI FinFET at 14 nm technology node is investigated. Based on the device TCAD model, well-calibrated by the experimental data, it is found that the spacer presents the enhancement on single event transient (SET) compared with no spacer configuration. For single spacer configuration, due to enhanced gate control capability and fringing field, the increments in SET current peak and collected charge for HfO2 are the least with 2.21%, 0.97%, respectively. Four possible dual ferroelectric spacer configurations are proposed. The placement of ferroelectric spacer at S side and HfO2 spacer at D side brings to weaken SET with the variation in current peak and collected charge by 6.93%, 1.86%, respectively. The reason may be its enhanced gate controllability over the S/D extension region, which improves the driven current. With linear energy transfer increasing, SET current peak and collected charge present the trend of increase while the bipolar amplification coefficient reduces.

Verilog-A модель эффекта вымораживания примеси в LDD областях при криогенных температурах

The article shows the practical implementation of the impurity freeze-out effect in the lightly-doped areas of the drain and source (LDD) in the Verilog-A model of the resistor. This model is based on a theoretical understanding of the freeze-out effect at cryogenic temperatures and data from the TCAD simulation of a MOSFET. The TCAD simulation data were represented by transconductance characteristics of n- and p-channel transistors Id(Vg) in linear mode (Vd=0.1 V) at temperature range from -200 °C to 27 °C for transistors with dimensions 10 um × 10 um. The model is applicable to the use as part of a macromodel of a MOSFET transistor for a CMOS bulk process with a supply voltage of 1.8 V and a minimum channel length of 0.18 um. Since the model is based on a limited set of TCAD modeling data, this version is the basis on which it is possible to build a geometrically scalable model that will be valid over the entire range of drain voltages.