Low-Voltage Logic Gates based on Vertical GAA Nanotransistors

Abstract

The issues of numerical simulation of low-voltage logic gates based on silicon vertical surrounding gate CMOS nanotransistors with a conical working area circuits are discussed. Using the TCAD instrument process modeling program, numerical studies of conical prototypes have been performed. The electrophysical characteristics in the control voltage range from 0 to 0.6 V are characterized by a higher transistor current, a maximum Ion/Ioff current ratio, a low leakage current and a slope of the subthreshold characteristic close to the theoretical aisle. 3D TCAD models of three basic logic gates on vertically arranged transistors of n-and p-types have been developed for an optimized ratio of the diameters of the working area of 8.4/10 nm and the length of the working area of 22 nm. Their electro-physical characteristics are numerically investigated at control voltages of 0.6 V and a frequency of 20 GHz. The gate models demonstrate picosecond delays and low power consumption. The promising characteristics of the proposed transistors and valves based on them, such as a high degree of integration, high performance and low cost, open the way to the development of 3D integrated circuits of the next generation.