Abstract
Methodological and practical aspects of testing microcontrollers for resistance to power analysis reengineering are considered. A model of quantitative assessment of durability is proposed, based on the construction of a relative parameter variance diagram of an operation with data. Within the framework of the model, a criterion has been introduced that allows comparing the durability of various devices. The key provisions of the methodology for testing devices on the power consumption channel have been developed. Using the example of testing one of the microcontrollers, the procedure for determining the resistance to extracting internal memory data is presented. Based on the results of the analysis, conclusions are formulated about the possibility of safe operation with this microcontroller in information systems.
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