Tapped Delay Line Research Articles

A resource-saving dual channel time-to-digital converter with shared tapped delay line in FPGAs

A resource-saving dual channel time-to-digital converter (TDC) in field programmable gate array (FPGA) is presented in this paper. The presented TDC is formed by cascading a channel waveform generator (CWG) and a tapped delay line. Specifically, the CWG can generate six types of waveforms with different transition edges to propagate on tapped delay line according to the different assertion times of two hit signals. Besides, a pipelined encoding module is designed to detect the positions of multiple transition edges on tapped delay line precisely so that the six types of waveforms can be identified and the two hit signals can be distinguished and measured. Since the measurements of two hit signals share one tapped delay line, the TDC based on CWG (CWG-TDC) is a resource-saving dual channel TDC. To evaluate the performance of CWG-TDC, time intervals from 10ns to 200ns were measured on a Xilinx's 40nm Virtex-6 development board. In CWG-TDC, channel 1 and channel 2 can achieve LSB of 9ps, the highest RMS precision of 6.2ps. The consistency between experimental results and theoretical analysis shows that the presented CWG-TDC can not only achieve high RMS precision but also achieve resource-saving.

Phase-Only Space-Time Adaptive Processing

Space-time adaptive processing (STAP) is a well-known and effective method to detect targets, obscured by interference, from airborne radars that works by coherently combining signals from a phased antenna array (spatial domain) with multiple radar pulses (temporal domain). As widely demonstrated, optimum STAP, in the sense of maximizing the output signal to interference plus noise ratio (SINR), is a coherent, linear, transversal filter (i.e., tapped delay line), that can be synthesized by a complex-valued weight vector. This paper extends previous work that focused on adaptive spatial-only nulling; it derives the optimum phase-only STAP, namely, the optimal weight vector that maximizes the SINR subject to the constraint it belongs to the $N$ -torus of phase-only complex vectors, where $N$ is the number of spatio-temporal degrees of freedom. Because this problem does not admit a closed-form solution, it is solved numerically using the phase-only conjugate gradient method (CGM). The effectiveness of phase-only STAP is demonstrated using both SINR values and receiving beampattern shape, comparing it with the optimum fully-adapted STAP and the nonadapted beam former responses as well as other possible counterparts. Additionally, several analyses of practical utility also demonstrate the benefits provided by phase-only STAP.

Time-to-Digital Converter IP-Core for FPGA at State of the Art

The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time-Mode (TM) circuits almost unfeasible. In particular, in Programmable Logic (PL) devices, such as FPGAs, the operation of the logic is usually synchronous with the system clock. However, it can happen that a very high-performance specifications demands to abandon this paradigm and to follow an asynchronous implementative solution. The main driver forcing the use of programmable logic solutions instead of tailored Application Specific Integrated Circuits (ASIC), best suiting an asynchronous design, is the request coming from the research community and industrial R&D of fast-prototyping at low Non Recursive Engineering (NRE) costs. For instance in the case of a high-resolved Time-to-Digital Converter (TDC), a signal clocked at some hundreds of MHz implemented in FPGA allows implementing a TDC with resolution at ns. If a higher resolution is required, the signal frequency cannot be increased further and one of the aces up the designer's sleeve is the propagation delay of the logic in order to quantize the time intervals by means of a so-called Tapped Delay-Line (TDL). This implementation of TDL-based TDC in FPGAs requires special attention by the designer both in making the best use of all available resources and in foreseeing how signals propagate inside these devices. In this paper, we investigate the implementation of a high-performance TDL-TDC addressed to 28-nm 7-Series Xilinx FPGA, taking into account the comparison between different technological nodes from 65-nm to 20-nm. In this context, the term high-performance means extended dynamic-range (up to 10.3 s), high-resolution and single-shot precision (up to 366 fs and 12 ps r.m.s respectively), low differential and integral non-linearity (up to 250 fs and 2.5 ps respectively), and multi-channel capability (up to 16).

Emulation of Radio Technologies for Railways: A Tapped-Delay-Line Channel Model for Tunnels

Radio access technologies (RATs) are a key topic in railways, enabling them a better service rendering in terms of shorter headways between trains, higher safety levels and higher customer satisfaction. Very often, these railway RATs need a lot of time to be developed, tested and put into service, which implies a lack of efficiency and bottlenecks in the evolution of railway systems. To solve this situation, an emulation platform that considers both the physical layer and the network (this is, able to emulate the end-to-end chain) is envisaged in the EmulRadio4Rail project. Therefore, the physical layer of many railway scenarios must be emulated, which is a remarkable challenge because railways are very diverse. We see Tapped-Delay Lines (TDL) models as the most efficient way for emulation with the available hardware. In the literature, there are many TDL-based channel models for all the scenarios we considered but one: tunnels. Therefore, in order to fill this gap, we develop a novel TDL model for railway tunnels, considering the impact of the rolling stock (both high-speed railway (HSR) and subway trains). The proposed model allows the full characterization of this scenario in terms of power-delay-profile (PDP), Doppler spectrum and fading characteristics.

A novel pipelined neural FIR architecture for nonlinear adaptive filter

This paper presents a novel adaptive pipelined neural finite impulse response (PNFIR) filter for nonlinear signal processing. Unlike traditional pipelined recurrent neural network (PRNN), each module of the PNFIR filter is a simple architecture that includes a standard FIR filter followed by a nonlinear activation function. The complete design of proposed filter includes two subsections: The nonlinear part consists of neural FIR (NFIR) modules which is interconnected in a chained form and simultaneously executed in a parallel fashion; the linear subsection is a tapped-delay-line (TDL) linear combiner. Based on convex combination architecture, the adaptive algorithm derived from the gradient descent approach is utilized to update weights of the nonlinear and linear parts. Moreover, the analysis of stability conditions and computational complexity is also presented. Numerous simulation experimental results on nonlinear dynamic systems identification, speech signal and chaotic time series prediction show that the proposed PNFIR filter has simpler architecture, faster convergence rate, and lower computation complexity than the PRNN and joint process filter using pipelined feedforward second-order Volterra architecture (JPPSOV).

Tunable optical single-sideband generation for OOK and PAM4 data channels using an optical frequency comb and nonlinear wave-mixing.

We experimentally demonstrate tunable optical single-sideband (SSB) generation using a tapped-delay-line (TDL) optical filter for 10 and 20 Gbit/s on/off-keying (OOK) signals and a 20 Gbit/s four-level pulse-amplitude-modulated (PAM4) signal. The optical SSB filter is realized by using an optical frequency comb, wavelength-dependent delay, and nonlinear wave-mixing to achieve the TDL function. Moreover, SSB tunability is achieved by adjusting the amplitude, phase, frequency spacing, and number of selected optical frequency comb lines. We show that the one-sideband suppression of a double-sideband (DSB) channel can be enhanced as the number of taps is increased; however, we do measure a ∼1.5% error-vector-magnitude penalty. Furthermore, we demonstrate that the chromatic-dispersion-induced penalty after 80 km standard-single-mode-fiber transmission of a 10 Gbit/s SSB OOK signal without chromatic dispersion compensation has been reduced by >3dB when compared to DSB.

Sparse Array Beamforming Design for Wideband Signal Models

We develop sparse array receive beamformer design methods achieving maximum signal-to-interference plus noise ratio (MaxSINR) for wideband sources and jammers. Both tapped delay line (TDL) filtering and the DFT realizations to wideband array processing are considered. The array sparsity stems from the limited number of available RF transmission chains that switch between the sensors, thereby configuring different arrays at different times. The sparse array configuration design problem is formulated as a quadratically constraint quadratic program (QCQP) and solved by using SDR (semidefinite relaxation). A computationally viable approach through SCA (successive convex relaxation) is also pursued. In order to realize an implementable design, in presence of missing autocorrelation lags, we propose parameter-free block Toeplitz matrix completion to estimate the received data correlation matrix across the entire array aperture. It is shown that the optimum wideband sparse array effectively utilizes the array aperture and provides considerable performance improvement over suboptimal array topologies.

Validation of cloud‐radio access network control unit with intra‐PHY architecture: Hardware‐in‐the‐loop framework based on frequency‐domain channel models

AbstractIn this article, a signal processing framework for hardware‐in‐the‐loop (HIL) validation of the cloud‐radio access network (C‐RAN) control unit (CU) with a crosshaul intra‐PHY architecture split is evaluated. The framework is based on the assumption that data exchanged over the crosshaul interface between the lower and higher parts of the physical layer have the form of frequency‐domain orthogonal frequency division multiplexing (OFDM) subcarriers. Therefore, it is proposed to simulate the effects of a wireless fading channel directly in the frequency domain, instead of the conventionally selected time domain. This approach leads to complexity reduction of the channel simulation model by minimizing the number of required FFT/IFFT operations, at the cost of simulation accuracy in high‐mobility and high‐delay spread scenarios. Analysis of bit error ratio (BER) and block error ratio (BLER) metrics obtained using both time‐ and frequency‐domain channel models is presented in order to validate the proposal and evaluate the accuracy loss caused by the usage of nonideal frequency‐domain models. The frequency‐domain methods are compared against the conventional wide sense stationary uncorrelated scattering (WSSUS) model implementation based on the tapped delay line (TDL). It is shown that the utilization of improved frequency‐domain models instead of the block‐fading model substantially decreases the BER/BLER prediction error in specific scenarios.

A Step Towards the Development of Socio-cognitive Agent

The embodiment of consciousness in socio-cognitive agents play a significant role in their acceptance as co-partners. Man-machine social interaction’s success is based on the agent’s generated believable behaviors. In this regard, such an agent needs to generate realistic beliefs, intentions, goals, self-regulation, verbal, and non-verbal communication (including gestures) according to the context of ongoing interaction is very important. This study hypothesizes that the implementation of the Theory of mind (TOM) may allow the agent to change its intentions, beliefs, and desires by predicting the existing perspective and mental states of the other agents involved in the given social interaction. To study the complexity of dynamics in a social context we have taken the case study of the ‘paper-scissor-rock’ game and developed a cognitive agent capable of using gestures for non-verbal communication following the Theory of mind. This work is in progress and is being developed on the iCub robot simulation. We have used tapped delay line neural networks as the basis for reinforcement learning and strategic planning. This paper will report the cognitive model, neural network initial results obtained.

NARX NETWORK BASED DATA-DRIVEN ALGORITHM FOR DETECTION OF TRAY FAULTS IN NONLINEAR DYNAMIC DISTILLATION COLUMN

Efficient monitoring of highly complex process industries is essential for better management, safer operations and high-quality production. Timely detection of various faults helps to improve the performance of the complex industries, prevent various unfavorable consequences and reduce the maintenance cost. Fault Detection and Diagnosis (FDD) for process monitoring and control has been an active field of research for the past two decades. Distillation columns are inherently nonlinear, and thus to have an accurate and robust performance, the fault detection methods should be based on nonlinear dynamic methods. The paper presents a robust data-driven fault detection approach for realistic tray upsets in the distillation column. The detection of tray faults in the distillation column is conducted by Nonlinear AutoRegressive with eXogenous Input (NARX) network with Tapped Delay Lines (TDL). Aspen Plus® Dynamic simulation has been used to generate normal and faulty datasets. The study shows that the proposed method can be used for the detection of tray faults in distillation column for dynamic process monitoring. The performance of the proposed method has been evaluated by the Missed Detection Rate (MDR) and the Detection Delay (DD).

Measurement‐based determination of parameters for non‐stationary TDL models with reduced number of taps

This study proposes a new strategy of extracting parameters for tapped delay line (TDL) channel models from vehicle to infrastructure channel measurements. The proposed approach is based on an already existing method to derive parameters for a non-stationary model using first-order Markov chains. It will be shown that with the proposed method, the number of taps necessary to regenerate the delay spread of a channel can be significantly reduced. An approach will be discussed to evaluate the performance of the model. The feasibility of the method will be confirmed using channel sounding measurements.

Enhancements on Coding and Modulation Schemes for LTE-Based 5G Terrestrial Broadcast System

Broadcasting and broadband network is moving towards integration and LTE-based 5G terrestrial broadcast is now researched in Release 16 in Third Generation Partnership Project (3GPP) standardization meetings. However, the work scope of LTE-based 5G terrestrial broadcast focuses on specifying new numerologies and some minor improvement on cell acquisition subframe, which is insufficient. In this paper, limitations in coding and modulation schemes of LTE-based 5G terrestrial broadcast system, e.g., Turbo codes and Quadrature Amplitude Modulation (QAM), are detailedly analyzed. To further enhance the spectrum efficiency of LTE-based 5G terrestrial broadcast system, LDPC (Low Density Parity Check) codes from 5G new radio (NR) standard and newly designed non-uniform constellations (NUCs) are adopted in this paper to replace Turbo codes and QAM respectively. Extensive simulations and complexity analysis show that the proposed LDPC coding and NUC modulation scheme, either standalone or combined, can provide significant performance gain over Additive White Gaussian Noise (AWGN) and Tapped Delayline (TDL) channels, without additional complexity. To summarize, this paper investigates the weakness of the coding and modulation schemes in current systems and provides potential alternatives for the enhanced future broadcast in 3GPP standard.

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

Technology Independent ASIC Based Time to Digital Converter

This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces design time. The proposed design flow is fully automated using TCL scripting and standard CAD tools configuration files. The TDC is based on a Tapped Delay Line architecture and explores the use of Structured Data Path (SDP) as a way to improve the TDL linearity by homogenizing the routing and parasitic capacitances across the multiple TDL's steps. The studied approach also secures a stable, temperature independent measurement operation. The proposed TDC architecture was fabricated using TSMC 180nm CMOS process technology, with a 50MHz reference clock and a supply voltage of 1.8V. The fabricated TDC achieved an 111ps RMS resolution and a single-shot precision of 54ps (0.48 LSB) and 279ps (2.51 LSB), with and without post-measurement software calibration, respectively. The DNL across the channel is mostly under 0.3 LSB and a maximum of 8 LSB peak-to-peak INL was achieved, when no calibration is applied.

An optimized MAC based architecture for adaptive digital filter

Filter design in signal processing field plays a vital role in achieving low power dissipation, which is essential for portable gadgets. This paper proposes an effective flexible FIR filter structure, which is adaptive and utilizes multiply–accumulate (MAC) core. Most common algorithm for filter coefficient optimization includes least mean square (LMS) and recursive least square (RLS). Though the performance of the recursive least square (RLS) algorithm is superior as compared to the least mean square (LMS); because of higher arithmetic complexity in design, it has not been preferred for real time applications. The fundamental filter has used a LMS based tapped delay line filter, which is practically a feasible choice for adaptive filtering algorithm in order to attain lesser computation. In the proposed work, the adjustable coefficient filters using an optimized LMS approach has been implemented for the utilization of determining the unexplored system. The filter tap considered here is a 32-tap and its analysis and synthesis has been carried out using hardware description language (HDL) programming and synthesized in field programmable gate array (FPGA) devices. The placement and post routing design has offered good performance in terms of utilized resources. The implemented filter architecture requires 80% reduction in resources and has enhanced the clock frequency by about five times when examined with the reported architecture.

Exact expectation analysis of the LMS adaptive identification of non‐linear systems

Most adaptive filtering schemes employ the tapped-delay line. In part, such a fact can be explained by the assumption that the plant they intend to estimate is linear. Although such a hypothesis can be reasonable if the input signal is constrained to a certain range, sometimes it may not be valid. In this last case, the performance and stability guarantees provided by stochastic models that presume linearity of the ideal system are no longer valid. This Letter advances an analytic model of the least-mean-square (LMS) learning capabilities when the ideal system is not linear, with the additive noise including non-linear functions of the input samples. The proposed analysis does not assume neither that the excitation signal is statistically independent of the adaptive weights, nor that the additive noise is white and/or independent of input data. Furthermore, it can be applied to non-Gaussian and/or non-white input signals. Simulations show that the advanced model is more accurate than traditional approaches.

A High-Linearity Vernier Time-to-Digital Converter on FPGAs With Improved Resolution Using Bidirectional-Operating Vernier Delay Lines

Time-to-digital converters (TDCs) act as a core component in many timing-critical systems. Tapped delay line is the most widely used style for the field-programmable gate-array (FPGA)-based TDCs, but it suffers from several intractable problems such as poor nonlinearity and long delay-line occupation. Recently, a new ring-oscillator-based Vernier TDC circuit using carry chains was demonstrated to have much smaller nonlinearity with a much shorter delay line. Since the used delay line is not compensated, the timing jitter increases (or the precision degrades) remarkably when the oscillation number is large. This would incur undesirable lower resolution selection to maintain acceptable precision. In this article, a novel bidirectional-operating Vernier delay line structure is proposed to reduce the required oscillation number during the fine time measurement. Traditionally, for the Vernier delay line, the fast signal propagates along the slow delay line, while the slow signal propagates along the fast delay line, to which we call the normal Vernier delay line. The new structure proposes two parallelized Vernier delay line, consisting of one normal Vernier delay line and another abnormal Vernier delay line. The term “abnormal” refers to that the fast and slow signals are unusually fed to the fast and slow delay lines, respectively. A prototype TDC circuit based on this new method was implemented on a Stratix III FPGA. Test results demonstrate that by adopting the proposed novel circuit architecture, both the resolution and the root-mean-square error can be improved from the 30–40-ps level to the 20–30-ps level.

Statistical Sparse Channel Modeling for Measured and Simulated Wireless Temporal Channels

Time-domain wireless channels are generally modeled by Tapped Delay Line (TDL) model and its variants. These models are not effective for channel representation and estimation when the number of multipath taps is large. Compressive sensing (CS) provides a powerful tool for sparse channel modeling and estimation. Most of the research has been focusing on sparse channel estimation, while sparse channel modeling (SCM) is rarely considered for centimetre-wave channels. In this paper, we investigate statistical sparse channel modeling, using both measured and simulated channels over a frequency range of 6 to 8.5 GHz. We first introduce the triple equilibrium principle to explore the trade-off between sparsity, modeling accuracy, and algorithm complexity in SCM, and provide a methodology for characterizing the sparsity of time-domain channels using single-measurement-vector compressive sensing algorithms. Using mainly the selected wavelet dictionary and various CS reconstruction (aka recovery) algorithms, we then present comprehensive statistical sparse channel models, including channel sparsity, magnitude decaying profile, sparse coefficient distribution and atomic index distribution. Connections between the parameters of conventional TDL and sparse channel models are mathematically established. We also propose three methods for generating simulated channels from the developed sparse channel models, which validates their effectiveness.

New Concept of Combined Microwave Delay Lines for Noise Radar-Based Remote Sensors.

Delay lines with a tunable length are used in a number of applications in the field of microwave techniques. The digitally-controlled analogue wideband delay line is particularly useful in noise radar applications as a precise detector of movement. In order to perform coherent reception in the noise radar, a delay line with a variable delay value is required. To address this issue, this paper comprises a new concept of a digitally-controlled delay line with a set of fine distance gates. In the paper, a solution for micro-movement detection is proposed, which is based on direct signal processing in the time domain with the use of a microwave analogue correlator. This concept assumes the use of a microwave analogue tapped delay line structure. It was found that the optimal solution for a noise radar with an analogue signal correlator is a combined delay line consisting of switched reference sections, a tapped delay line, and a precision phase shifter. The combined delay line presented in this paper is dedicated to serving as the adjustable reference delay for a noise radar intended for the detection of micro-movement. The paper contains the calculation results and delay line implementation for a given example. The new structure of the analogue tapped delay line with the calculation of optimal parameters is also presented. The precise detector of movement can be successfully used for the remote sensing of human vital signs (especially through-the-wall), e.g., breathing and heart beating, with the simultaneous determination of position.

A 3.0-ps rms Precision 277-MSamples/s Throughput Time-to-Digital Converter Using Multi-Edge Encoding Scheme in a Kintex-7 FPGA

In a field-programmable gate array (FPGA)-based time-to-digital converter (TDC), the hit signal to be measured launches out a segment of the clock-like signal propagating along the tapped delay line (TDL). If every edge of the clock-like signal in the TDL status is identified by the encoder, parallel multiple measurements can be achieved to improve the TDC time precision. In this article, we propose a bubble-proof multi-edge encoding scheme by hardware in pipeline fashion, which can achieve 277-MSamples/s measurement throughput on a Kintex-7 FPGA. Based on the encoding scheme, TDCs with 1-, 2-, 4-, 6-, and 8-edge multiple measurements are sequentially implemented. The corresponding average rms precisions measuring time intervals from 0 to 50 ns are evaluated as 8.2, 4.8, 3.5, 3.1, and 3.0 ps, respectively. The test results confirm that the proposed TDC with a multi-edge encoding scheme can effectively improve TDC time precision without adding TDC measurement dead time. Its resource-saving feature also makes it feasible for multi-channel TDC integration.