Tapped Delay Line Research Articles

A 19 ps Precision and 170 M Samples/s Time-to-Digital Converter Implemented in FPGA with Online Calibration

This paper presents a 19 ps precision and 170 M samples/s time-to-digital converter (TDC) in FPGA. Through the direct count method and tapped delay line method, the coarse count and fine count can be extracted, respectively. The direct count is realized by the 350 M clock and the tapped delay line is constructed by the CARRY4 block. The ones-counter encoder is used to convert the thermometer code with bubble errors into binary code, which is applicable to all the FPGA chips. This work not only explains the schematic of the ones-counter encoder, but also shows how to configure it. Owing to the inconsistency of delay elements caused by process, bin-by-bin calibration is utilized to improve the differential nonlinearities (DNL) and integral nonlinearities (INL) of the TDC. A novel method was developed to compensate the influence of voltage and temperature. As the delay elements vary with voltage and temperature, a frequency counter is used to extrapolate and compensate its effect on the delay line. All of the above strategies use online calibration and improve the precision and sampling rate of TDC. The experimental results show the least significant bit (LSB) achieves 17.4 ps, the DNL is within [−0.90, 1.67] LSB, and the INL is in the range of [−1.90, 3.31] LSB.

Activity detection for enhanced configured-grant: A practical perspective

We try to extend the current configured-grant (CG) uplink scheme in 5G New Radio (NR) to support massive potential users and study activity detection under this scenario. Characteristics of the continuously varying channel and the multiple repetition scheme are utilized to improve the detection accuracy, which can be an enhancement to existing activity detection algorithms. Numerical results under 3GPP TDL (Tapped Delay Line) fading channel show the superiority of our algorithm. And system-level simulation reveals that enhancements on activity detection can improve reliability and reduce latency.

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection

A field-programmable gate array (FPGA) high-resolution time-to-digital converter (TDC) based on phase-wrapping, sorting, and selection to achieve an extremely fine bin size of 1 ps is proposed in this paper. Based on Nutt interpolation method, a wide measurement range with a high resolution can be realized at the same time. The input signal is fed into tapped delay lines (TDL) with regularized and automated cell placements to generate a multitude of delayed signals with plenty of regularized phase shifts. Due to periodicity, those phase shifts will be equivalently wrapped within a reference clock period and then phase sorting, ROM-based selection are applied to construct a merged TDL with uniform phase division across the reference clock period. The FPGA TDC was implemented successfully on both Altera Stratix IV to achieve a resolution as fine as 1ps with a measurement range of 1s. The short-range integral non-linearity errors (INL) are measured as -1.470 – 1.676 LSB for Stratix IV to demonstrate its excellent linearity.

Neural Approximators for Variable-Order Fractional Calculus Operators (VO-FC)

The paper presents research on the approximation of variable-order fractional operators by recurrent neural networks. The research focuses on two basic variable-order fractional operators, i.e., integrator and differentiator. The study includes variations of the order of each fractional operator. The recurrent neural network architecture based on GRU (Gated Recurrent Unit) cells functioned as a neural approximation for selected fractional operators. The paper investigates the impact of the number of neurons in the hidden layer, treated as a hyperparameter, on the quality of modeling error. Training of the established recurrent neural network was performed on synthetic data sets. Data for training was prepared based on the modified Grünwald-Letnikov definition of variable-order fractional operators suitable for convenient numerical computing without memory effects. The research presented in this paper showed that recurrent network architecture based on GRU-type cells can satisfactorily approximate targeted simple yet functional variable-order fractional operators with minor modeling errors. In addition, the research also compares the presented solution with basic and recurrent neural networks that utilize Tapped Delay Lines (TDL) in their structure. The presented solution is a novel approach to the approximation of VO-FC operators. It has the advantage of automatic selection of neural approximator parameters by optimization based on data customized for specific requirements.

An Efficient TDC Using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA

FPGA-based time-to-digital converters (TDCs) are required to be accurate, linear, and fast, while at the same time employing a reduced number of resources. Pushing these requirements to the limit is challenging, although it is constantly required by many applications. This article presents a dual-mode tapped-delay-line (TDL)—propagating 1’s and 0’s in alternating measurement cycles—architecture for a field-programmable gate array (FPGA)-based TDC that complies with the mentioned specifications. The dead-time of the proposed TDC is reduced to one system clock cycle by using a toggling input stage and a dual-mode counter-based encoder. To improve the TDC linearity, the TDL sampling sequence is tuned separately for each operating mode. The presented architecture employs a low-resources dual-mode combinatory encoder of one- and zero-counters to remove the bubbles and cover both operating modes. A dual-mode bin-width calibration has been carried out to improve the TDC performance in each mode. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA. Experimental results have shown a differential nonlinearity (DNL) within [−0.71 1.05] least significant bit (LSB) and an integral nonlinearity (INL) within [−0.85 0.86] LSB for the propagation of 1’s. DNL and INL are within [−0.73 1.06] LSB and [−1.17 0.04] LSB, respectively, for the propagation of 0’s. The LSB size is 22.1 ps and the TDC precision is 22.35 ps. A comparison with recently published state-of-the-art FPGA-based TDCs is provided at the end of the article.

Real-time ray-based channel generation and emulation for UAV communications

A real-time ray-based hardware emulator for Unmanned Aerial Vehicle (UAV) communication channels which suits for the Three-Dimensional (3D) dynamic scenarios and considers the movements of both terminals is developed in this paper. The time-variant channel parameters, i.e., ray delay, ray gain, and ray Doppler frequency are precalculated in the host by using the Ray Tracing (RT) method. Meanwhile, RT simulation dramatically increases the number of valid rays. To address the problem of resource limitation and huge computational burden in the implementation, an efficient ray coefficients generation method based on iteration is proposed and implemented. With the advantages of low cost and high flexibility, a Software Defined Radio (SDR) hardware platform is used to emulate the ray-based UAV channels by utilizing the compact architecture including the Time-Division (TD) scheme and Tapped-Delay Line (TDL) for channel convolution. Finally, hardware measurement results demonstrate that the properties of emulated channel, i.e., Power Delay Profile (PDP) and Doppler Power Spectrum Density (DPSD) consist with the simulated ones, which verifies the correctness of hardware implementation. The proposed channel emulator provides an efficient way for optimization, verification, and evaluation of UAV communication systems.

Performance analysis and IP Core Implementation of two high performance time-to-digital converters on Xilinx 7-series FPGA

After extensive research in the past decades, the design of field programmable gate array-based time-to-digital converters (TDC) with tapped delay line (TDL) architecture has become relatively mature, and the performance that can be achieved has also been reasonably high. This paper first presents a comprehensive analysis of measurement uncertainty of two different multi-interpolation TDL based TDCs. By executing multiple time interpolations within one clock cycle, the discrepancy between the resolution improvement and precision improvement is quantitatively analyzed. Therefore, the contributions of major error sources can be clearly understood, which is helpful for TDC designers to predict the performance that their TDCs can achieve. Thanks to the structural characteristics of TDL-TDCs and the build-in function of relatively placed macro (RPM) in Xilinx Vivado Design Suite, the implementations of these two TDCs can be packaged as intellectual property (IP) cores. Since the major building elements and their relative positions can be assigned with pre-established constraints, the high TDC performances can be maintained when the IP cores are instantiated. With the knowledge of TDC architectures and factors affecting performance introduced in this paper, end-users can easily configure the IP cores to meet their requirements without the need of knowing technique details.

Efficient Routing Algorithm using MLP and RBX in a Four Model Neural Networks

Two important paradigms which are contradicting by nature namely: the efficient routing information diffusion and adaptability to dynamic network conditions using wireless routing protocols have been researched in recent years. One way of solving this issue is by using the past experiences of a node in network traffic condition through intelligent algorithm to predict the network traffic condition in the future. In this methodology we propose an algorithm which is used to to predict one hop delay per packet during routing process using neural networking. The one hop delay that is predicted is then further used by the participating nodes for information diffusion during routing. Experimental analysis indicate that using tapped delay line radial basis function and tapped delay line multilayer perceptron, it is possible to predict mean delays as a time series. The inputs used for prediction are mean delay time series with traffic loads and mean delay time series itself. The pros and cons of the proposed work are also present in this paper.

Directivity enhancement with improved beamforming for physical layer ultra‐wideband communication by pulse shaping

SummaryIn this manuscript, a methodology of pulse shape modification is used for the directivity enhancement of ultra‐wideband (UWB) beam formation, to suppress the interference due to co‐existing narrowband communications with UWB signals. We propose that the modified pulse shaping produces more direct beam patterns for the tapped delay line antenna arrangements. These direct beam patterns are obtained for the smaller values of inter‐element spacing. This reduction of inter‐element spacing can provide more space for other development and compact the size of the any UWB antenna unit.

Experimental realization of integrated photonic reservoir computing for nonlinear fiber distortion compensation.

Nonlinearity mitigation in optical fiber networks is typically handled by electronic Digital Signal Processing (DSP) chips. Such DSP chips are costly, power-hungry and can introduce high latencies. Therefore, optical techniques are investigated which are more efficient in both power consumption and processing cost. One such a machine learning technique is optical reservoir computing, in which a photonic chip can be trained on certain tasks, with the potential advantages of higher speed, reduced power consumption and lower latency compared to its electronic counterparts. In this paper, experimental results are presented where nonlinear distortions in a 32 GBPS OOK signal are mitigated to below the 0.2 × 10-3 FEC limit using a photonic reservoir. Furthermore, the results of the reservoir chip are compared to a tapped delay line filter to clearly show that the system performs nonlinear equalisation.

Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device

This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolation (TI). In the first and second stages of the TI we have used the Vernier delay line and a single tapped delay line, respectively. This solution provides respectable metrological parameters without the need to use a clock signal, and significantly saves the logical resources of an integrated circuit (IC). The proposed method, generally based on two different variants of the discrete delay line, is easy to design and implement in digital ICs. For experimental verification, the TDC was implemented in a single programmable device from family Virtex-7 (Xilinx).

Demonstration of QPSK data correlation and equalization using a tunable optical tapped delay line based on orbital angular momentum mode delays

We demonstrate a tunable optical tapped delay line (OTDL) using delays based on orbital angular momentum (OAM) modes to perform data correlation and equalization for a quadrature phase-shift-keyed (QPSK) signal. The system: (i) creates N signal replicas as N taps on different OAM modes through mode multicasting, (ii) tunes the complex tap weights (i.e., amplitude and phase of the modes), (iii) applies a tunable mode-dependent delay to each replica, and (iv) coherently combines the taps in order to realize the OTDL functions of correlation and equalization. The experiment results: (i) identify the correlation occurrence of a sequence of 2 or 3 symbols in an incoming 10 or 20 Gbaud QPSK signal, and (ii) equalize the distortion caused by chromatic dispersion for a 20-Gbaud QPSK data signal and reduce error vector magnitude (EVM) from ∼25.4 to ∼12.9%.

Readout Electronics Prototype of TOF Detectors in CEE of HIRFL

In the Cooling storage ring External-target Experiment (CEE) in heavy ion research facility in Lanzhou (HIRFL), multigap resistive plate chambers (MRPCs) detectors are used for high-precision time-of-flight (TOF) measurement to identify the scattered particles after the ion beam hits the target. Regarding the external TOF (eTOF) and 2/3 internal TOF (iTOF) detectors, a ~25-ps rms time precision is required for the readout electronics, whereas for the other 1/3 iTOF detectors, a ~10-ps rms precision is required. A readout electronics prototype was designed, including the front-end electronics (FEE) based on analog signal amplification, discrimination, and the time-to-digital module (TDM), based on field-programmable gate array (FPGA) time-to-digital converter (TDC), to achieve high-precision time measurement. PreAmplifier-DIscriminator (PADI) is used in the design of the FEE, while an FPGA TDC, based on tapped delay line (TDL) structure, with a time precision performance better than 5-ps rms, is implemented in the TDM, as well as the trigger matching circuit and other control logic. The performance of the whole system was tested under different input signal charges and the results indicated that the time precision is better than 10-ps rms, which satisfies the application requirements.

Arbitrary free spectral range control of optical frequency combs based on an optical tapped delay line structure cascaded with a phase modulator

Arbitrary free spectral range control of optical frequency combs based on an optical tapped delay line structure cascaded with a phase modulator

Deep Learning-Based Joint Detection for OFDM-NOMA Scheme

Non-orthogonal multiple access (NOMA) technique has drawn much attention in recent years. It has also been a promising technique for the fifth-generation (5G) wireless communication system and beyond. In this letter, we develop a novel deep learning (DL) aided receiver for NOMA joint signal detection. The DL-based receiver serves as an end-to-end mode, which simultaneously fulfills the function of channel estimation, equalization, and demodulation. Compared with the traditional signal detection method for the NOMA scheme, the proposed deep learning method shows feasible improvement in performance and robustness with the tapped-delay line (TDL) channel model, which is adopted for the 5G communication environment.

Design of Nonlinear Autoregressive Exogenous Model Based Intelligence Computing for Efficient State Estimation of Underwater Passive Target.

In this study, an intelligent computing paradigm built on a nonlinear autoregressive exogenous (NARX) feedback neural network model with the strength of deep learning is presented for accurate state estimation of an underwater passive target. In underwater scenarios, real-time motion parameters of passive objects are usually extracted with nonlinear filtering techniques. In filtering algorithms, nonlinear passive measurements are associated with linear kinetics of the target, governing by state space methodology. To improve tracking accuracy, effective feature estimation and minimizing position error of dynamic passive objects, the strength of NARX based supervised learning is exploited. Dynamic artificial neural networks, which contain tapped delay lines, are suitable for predicting the future state of the underwater passive object. Neural networks-based intelligence computing is effectively applied for estimating the real-time actual state of a passive moving object, which follows a semi-curved path. Performance analysis of NARX based neural networks is evaluated for six different scenarios of standard deviation of white Gaussian measurement noise by following bearings only tracking phenomena. Root mean square error between estimated and real position of the passive target in rectangular coordinates is computed for evaluating the worth of the proposed NARX feedback neural network scheme. The Monte Carlo simulations are conducted and the results certify the capability of the intelligence computing over conventional nonlinear filtering algorithms such as spherical radial cubature Kalman filter and unscented Kalman filter for given state estimation model.

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

This article proposes a new calibration method, called the mixed-binning (MB) method, to pursue high-linearity time-to-digital converters (TDCs) for light detection and ranging applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in field-programmable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${{\bf DN}}{{{\bf L}}_{{\boldsymbol{pk}} - {\boldsymbol{pk}}}}$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${{\bf IN}}{{{\bf L}}_{{\boldsymbol{pk}} - {\boldsymbol{pk}}}}$</tex-math></inline-formula> are close to or even less than 0.05 LSB in multichannel designs.

Tunable optical second-order Volterra nonlinear filter using wave mixing and delays to equalize a 10-20 Gbaud 4-APSK channel.

We experimentally demonstrate a tunable optical second-order Volterra filter using wave mixing and delays. Wave mixing is performed in a periodically poled lithium niobate waveguide with the cascaded sum-frequency generation and difference-frequency generation processes. Compared to conventional optical tapped delay line structures, second-order taps are added through the wave mixing of two signal copies. We measure the frequency response of the filter by sending a frequency-swept sinusoidal wave as the input. The tap weights are tuned with a liquid-crystal-on-silicon waveshaper for different filter configurations. With the additional second-order taps, the filter is able to perform a nonlinear function. As an example, we demonstrate the compensation of a nonlinearly distorted 10-20 Gbaud 4-amplitude and phase shift keying signal.

A Broadband Multistage Self-Interference Canceller for Full-Duplex MIMO Radios

Full-duplex (FD) antenna arrays are desirable for expanding the channel capacity of wireless systems up to 2, which is particularly important in the crowded sub-6-GHz spectral bands. Conventional FD solutions based on circulators do not scale to antenna arrays due to the presence of significant mutual coupling between antenna elements. This article describes a two-stage self-interference cancellation (SIC) method that is suitable for FD arrays. The first-stage SIC uses a replica-antenna (RA)-based network that is passive and linear and can thus be placed before the low-noise amplifier (LNA) without significantly degrading receiver noise figure (NF) and linearity. The RA-based SIC also simplifies the hardware requirements for the second-stage SIC, which uses an analog tapped delay line (ATDL) network. The proposed two-stage SIC was realized using off-the-shelf components and tested in the 1–3-GHz range using strongly coupled pairs of ultrawideband antennas. Network analyzer measurements show 20–30 dB of SIC using the RA network over the entire frequency range and >20 dB of SIC using a single-stage ATDL SIC over instantaneous bandwidths of 0.53–0.65 GHz. The combined transmit (Tx)–receive isolation is 66.5, 73.5, and 85.8 dB around the center frequencies of 1, 2, and 3 GHz, respectively. The amount of isolation is shown to be sufficient for realizing practical FD wireless links at 2 GHz with reasonable Tx power levels (0 dBm).

Design of Time-to-Digital Converters for Time-Over-Threshold Measurement in Picosecond Timing Detectors

In picosecond timing detectors, the time over threshold (TOT) of detector signals is normally required to be measured to enhance the front-edge timing precision. The extremely narrow pulsewidth of these detector signals has posed challenges to the design of time-to-digital converters (TDCs) based on field programmable gate arrays (FPGAs) for TOT measurement. In this article, an FPGA-based tapped-delay-line (TDL)-type TDC is proposed to simultaneously measure the arrival time and TOT time of nuclear pulses. By propagating the hit signal along a single TDL, the proposed bubble-proof encoding scheme can extract the time information of two transitions of hit signal in one measurement. The minimum measurable TOT time is proved to be limited only by the electrical characteristics of low-voltage differential signaling (LVDS) receivers of FPGAs. Through the performance evaluation on the prototype with a Virtex Ultrascale + FPGA, where the minimum measurable TOT time can be as low as 370 ps, the rms precision reaches 3.0 ps for TOT time measurement. Given the pulsewidths ranging from 0.4 to 1.5 ns, the measured TOT time is highly consistent with the direct readout values from the oscilloscope in a wide temperature range. To apply the TDC into a microchannel plate photomultiplier tube (MCP-PMT)-based timing detector, the front-end electronics board with a dual-threshold TOT measurement is constructed. The joint beam test results show that the coincidence time resolution of two identical detector channels can be improved from 36.5 to 10.3 ps, which demonstrates the significance of TOT measurement to modern picosecond timing detectors.