System-on-chip Research Articles

Object Detection Using Adaptive Block Partition and RCNN Algorithm

Advancements in image and video processing are growing over the years for industrial robots, autonomous vehicles, cryptography, surveillance, medical imaging and computer-human interaction applications. One of the major challenges in real-time image and video processing is the execution of complex functions and high computational tasks. To overcome this issue, a hardware acceleration of different filter algorithms for both image and video processing is implemented on Xilinx Zynq®-7000 System on-Chip (SoC) device consists of Dual-core Cortex™-A9 processors which provides computing ability to perform with the help of software libraries using Vivado® High-Level Synthesis (HLS). The acceleration of object detection algorithms include Sobel-Feldman filter, posterize and threshold filter algorithms implemented with 1920 x 1080 image resolutions for real-time object detection. The implementation results exhibit effective resource utilization such as 45.6% of logic cells, 51% of Look-up tables (LUTs), 29.47% of Flipflops, 15% of Block RAMs and 23.63% of DSP slices under 100 MHz frequency on comparing with previous works. There are a few reasons why tracking is preferable over detecting objects in each frame. Tracking facilitates in identifying the identity of various items across frames when there are several objects. Object detection may fail in some instances, but tracking may still be achievable which takes into account the location and appearance of the object in the previous frame. The key hurdles in real-time image and video processing applications are object tracking and motion detection. Some tracking algorithms are extremely fast because they perform a local search rather than a global search. Tracking algorithms such as meanshift, Regional Neural Network probabilistic data association, particle filter, nearest neighbor, Kalman filter and interactive multiple model (IMM) are available to estimate and predict the state of a system.

LADA methodologies to localize embedded memory failure

Bitmap tool is commonly used by semiconductor design house to debug embedded memory failure as it is able to localize down to bit cell resolution with faster turnaround time as compared to hardware fault isolation methods. However, bitmap enablement requires tedious effort and high cost as it requires accurate logical-to-physical address scrambling information from memory IP provider to be successful. In this work, usage of hardware-based LADA fault isolation technique to debug system-on-chip (SOC) memory failure is discussed in term of implementation difficulty and success rate.

Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip

Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables the implementation and customization of the processor features to increase their reliability. Studies on hardened RISC-V processors facing harsh radiation environments apply fault tolerance techniques in the processor core and peripherals, exploiting system redundancies. In prior work, we present a hardened RISC-V System-on-Chip (SoC), which could detect and correct radiation-induced faults with limited fault awareness. Therefore, in this work, we propose solutions to extend the fault observability of the SoC implementation by providing error detection and monitoring. For this purpose, we introduce observation features in the redundant structures of the system, enabling the report of valuable information that supports enhanced radiation testing and support the application to perform actions to recover from critical failures. Thus, the main contribution of this work is a solution to improve fault awareness and the analysis of the fault models in the system. In order to validate this solution, we performed complementary experiments in two irradiation facilities, comprehending atmospheric neutrons and a mixed-field environment, in which the system proved to be valuable for analyzing the radiation effects on the processor core and its peripherals. In these experiments, we were able to obtain a range of error reports that allowed us to gain a deeper understanding of the faults mechanisms, as well as improve the characterization of the SoC.

Method for synthesizing a logic element that implements several functions simultaneously

Objectives. The basic element of a field-programmable gate array is a lookup table (LUT). While in canonical normal form LUTs generally implement only one logical function for a given configuration, in this case, there is always an inactive pass transistor element. Moreover, using a single LUT for a single function reduces system-on-a-chip (SoC) scalability. Therefore, the purpose of the present work is to develop a LUT structure for implementing several logic functions simultaneously on inactive transmitting transistors.Methods. The evolution of LUT structure is presented for three variables, in which the number of simultaneously implemented functions increases. To implement additional functions, the logical device was decomposed with a different number of variables. The structures were modeled in the Multisim electrical simulation system.Results. The presented simulation of more than two logic functions on inactive parts of the LUT shows the simultaneous operation of two and four logic functions. The complexity for a different number of variables and number of implemented functions is compared.Conclusions. The simulation results demonstrate the operability of LUT structures in which several logical functions are performed. Thus, when implementing additional functions in the new structure, a smaller number of transmitting transistors is required as compared to a conventional LUT, thus increasing device functionality. The presented solution can be used to increase the number of simultaneously implemented functions of the same variables, which can be important e.g., when implementing code transformations.

A Research on Operator Design Method for Health Detection SoC

Improving the efficiency of System-on-Chip(SoC) design has always been a hot topic in SoC design methods. The quality of SoC architecture design directly affects the core elements of SoC performance and cost. However, architecture design usually requires highly experienced and skilled personnel, which are scarce resources. Operators in SoC, like instructions in a CPU, are extracted from algorithms and are both universal and flexible. SoC can be designed based on operators, and algorithmic functions can be implemented through operators’ interconnection. In this paper, we propose an operator design method to improve the efficiency of SoC design. Additionally, we design algorithmic operators using pulse signal processing as an example to enhance the efficiency of designing health detection SoCs.

Continuous Integration for the Software and the Firmware of the New ATLAS Muon-Central- Trigger-Processor Interface (MUCTPI)

The new Muon-Central-Trigger-Processor Interface(MUCTPI) is part of the Phase-I upgrade of the ATLAS Level-1trigger system for Run 3 of the Large Hadron Collider at CERN.The new MUCTPI has three high-end FPGAs and one System-on-Chip (SoC). The FPGAs receive and process muon candidateinformation arriving on 208 high-speed optical serial links.Processed trigger information and summary data are sent to otherparts of the trigger and the data acquisition. The SoC controls,configures and monitors the hardware and the operation of theMUCTPI. The FPGA part of the SoC provides communicationwith the processing FPGAs, while the processor system runssoftware for communication with the run control system of theATLAS experiment. All software necessary to run the MUCTPI,including operating system and run control software is being builtusing continuous integration. CentOS Linux, cross-compilationand the existing framework for building of the ATLAS trigger anddata acquisition (TDAQ) software are being used in order todeploy the TDAQ software directly on the SoC. After thesuccessful use of continuous integration of the software, also thefirmware is being built using that scheme. This paper describes theadvantages of the use of continuous integration, our experience, aswell as the difficulties that needed to be overcome.

Texture Detection With Feature Extraction on Embedded FPGA

A feature extraction algorithm for texture detection oriented to its implementation on embedded electronics based on a Field-Programmable Gate Array (FPGA) is proposed in this paper. Local pre-processing with smart tactile sensors can help to improve dexterity in artificial hands. Simplicity is the goal in order to achieve a hardware-friendly strategy that can be replicated and integrated with another circuitry. This is interesting, considering that tactile sensors are arrays and FPGAs are capable of parallel execution. The proposal was tested with a custom smart tactile sensor mounted on a Cartesian robot to explore different textures. A comparison with a common feature extraction approach based on the fast Fourier Transform (FFT) computation was also made. In addition, the whole procedure is implemented on a System on Chip (SoC) with the feature extraction on the embedded FPGA and a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k-means</i> classifier on an ARM core. The proposed algorithm obtains the spatial frequency components of the tactile signal but not their power. Therefore, some information is lost with respect to that provided by the FFT. Nevertheless, an 89.17% accuracy of the proposed algorithm is obtained versus 91.4% with the FFT when twelve different textures are considered, including complex and fabric textures. There is a noticeable saving in power and hardware resources. In addition, since the size of the feature vector is much smaller, data traffic and memory usage is much lower, and the classifier can be simpler.

Split Boot—True Network-Based Booting on Heterogeneous MPSoCs

In the context of the High-Luminosity (HL) upgrade of the LHC, many custom ATCA electronics boards are being designed containing heterogeneous System-on-Chip (SoC) devices, more specifically the Xilinx Zynq UltraScale+ (ZUS+) family. While the application varies greatly, these devices are regularly used for performing board management tasks, making them a fundamental element in the correct operation of the board. The large number of hundreds of SoC devices creates significant challenges in their firmware deployment, maintenance, and accessibility. Even though U-Boot on ZUS+ devices supports network boot through the Preboot Execution Environment (PXE), the standard ZUS+ boot process contains application-specific information at earlier boot steps, particularly within the First Stage Bootloader (FSBL). This prevents the initialization of several devices from a universal image. Inspired by the PXE boot process on desktop PCs, this paper describes split boot, a novel boot method tailored to the specific needs of the ZUS+. All application-specific configuration is moved to a network storage device and automatically fetched during the boot process. We considered the entire process, from firmware and software development to binary distribution in a large-scale system. The developed method nicely integrates with the standard Xilinx development toolset workflow.

ACBN: Approximate Calculated Batch Normalization for Efficient DNN On-Device Training Processor

Batch normalization (BN) has been established as a very effective component in deep learning, largely helping accelerate the convergence of deep neural network (DNN) training. Nevertheless, its hardware architecture has not received much attention in the field of DNN on-device training processors. Several previous designs incur either high off-chip memory traffic or high circuit complexity, and hence have deficiencies in terms of hardware efficiency and performance. This article proposes approximately calculated BN (ACBN) to achieve a much better tradeoff between hardware efficiency and performance for DNN on-device training processors. The accuracy and convergence rate of the proposed ACBN have been extensively evaluated using four typical DNN models. Compared with the state-of-the-art reference design, the hardware simulation results show the proposed ACBN can at least reduce floating point operations by 22.2% and save external memory access by 33.3% on average. Moreover, the proposed ACBN introduces 63.6% data sparsity for the backward propagation of BN layers of VGG16 on average. To the best of our knowledge, we are the first to introduce data sparsity for the backward propagation of BN layers. The ACBN module is implemented on Zynq UltraScale <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> ZCU102 system-on-chip (SoC) field-programmable gate array (FPGA), and the results show that the implementation of ACBN hardware module saves 33.9% look-up table (LUT), 49.4% flip-flop (FF), 75% digital signal processor (DSP), and reduces the power by 12.4% compared with the reference design while achieving better performance.

An effective way to generate the shift timing constraints and sanity checks

Design for testability (DFT) is a technique, which facilitates a design to become testable after fabrication. As the technology node is shrinking, complexity of the system-on-chip (SoC) becomes high and inserting DFT and verifying its timing becomes complex. For these complex SoC, generating DFT timing constraints becomes difficult in shift mode and the time required for the generation of these timing constraints is also more. A new methodology proposed to overcome these issues. The main objective of this work is to propose the flow for generating DFT timing constraints for the complex SoC in shift mode, by dividing the design blocks into scan blocks and non-scan blocks. To target the whole design without getting all paths reported, relaxation of the setup, and hold time for non-scan blocks plays crucial role. If not, the time taken to generate DFT timing constraints would be more. Implemented methodology of this paper includes design setup, timing exceptions, and synopsys design constraints (SDC) generation for DFT timing. Design setup consists of all pre-requisites for design such as netlists, timing libraries, and exceptions. Synopsys primetime (PT Shell) is used for all the timing-related checks. Compared to conventional methods, the proposed flow reduces the overall time by 40% to generate constraints.

PulseDL-II: A System-on-Chip Neural Network Accelerator for Timing and Energy Extraction of Nuclear Detector Signals

Front-end electronics equipped with high-speed digitizers are being used and proposed for future nuclear detectors. Recent literature reveals that deep learning models, especially one-dimensional convolutional neural networks, are promising when dealing with digital signals from nuclear detectors. Simulations and experiments demonstrate the satisfactory accuracy and additional benefits of neural networks in this area. However, specific hardware accelerating such models for online operations still needs to be studied. In this work, we introduce <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PulseDL-II</i> , a system-on-chip (SoC) specially designed for applications of event feature (time, energy, etc.) extraction from pulses with deep learning. Based on the previous version, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PulseDL-II</i> incorporates a RISC CPU into the system structure for better functional flexibility and integrity. The neural network accelerator in the SoC adopts a three-level (arithmetic unit, processing element, neural network) hierarchical architecture and facilitates parameter optimization of the digital design. Furthermore, we devise a quantization scheme compatible with deep learning frameworks (e.g., TensorFlow) within a selected subset of layer types. We validate the correct operations of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PulseDL-II</i> on field programmable gate arrays (FPGA) alone and with an experimental setup comprising a direct digital synthesis (DDS) and analog-to-digital converters (ADC). The proposed system achieved 60 ps time resolution and 0.40% energy resolution at signal to noise ratio (SNR) of 47.4 dB.

Binary-Phase vs. Frequency Modulated Radar Measured Performances for Automotive Applications.

Radars have been widely deployed in cars in recent years, for advanced driving assistance systems. The most popular and studied modulated waveform for automotive radar is the frequency-modulated continuous wave (FMCW), due to FMCW radar technology's ease of implementation and low power consumption. However, FMCW radars have several limitations, such as low interference resilience, range-Doppler coupling, limited maximum velocity with time-division multiplexing (TDM), and high-range sidelobes that reduce high-contrast resolution (HCR). These issues can be tackled by adopting other modulated waveforms. The most interesting modulated waveform for automotive radar, which has been the focus of research in recent years, is the phase-modulated continuous wave (PMCW): this modulated waveform has a better HCR, allows large maximum velocity, permits interference mitigation, thanks to codes orthogonality, and eases integration of communication and sensing. Despite the growing interest in PMCW technology, and while simulations have been extensively performed to analyze and compare its performance to FMCW, there are still only limited real-world measured data available for automotive applications. In this paper, the realization of a 1 Tx/1 Rx binary PMCW radar, assembled with connectorized modules and an FPGA, is presented. Its captured data were compared to the captured data of an off-the-shelf system-on-chip (SoC) FMCW radar. The radar processing firmware of both radars were fully developed and optimized for the tests. The measured performances in real-world conditions showed that PMCW radars manifest better behavior than FMCW radars, regarding the above-mentioned issues. Our analysis demonstrates that PMCW radars can be successfully adopted by future automotive radars.

A Comprehensive Study of Different Techniques for Voltage References

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment.

SoC-based real-time SVM classification with integrated training using HLS and PYNQ

Support Vector Machines (SVM) are widely used techniques in the field of classification problems because of their ability to effectively deal with datasets that have complex non-linear structures and a high dimensionality. The compute-intensive training algorithm associated with SVM makes it challenging to keep an up-to-date model that accurately reflects the characteristics of newly arriving data points in real-time systems. This paper proposes a novel training algorithm for incremental learning from large datasets, based on a variant of Sequential Minimal Optimization (SMO). High-Level Synthesis (HLS) was used for implementing the Field Programmable Gate Array (FPGA) based Intellectual Property (IP) Core, which includes the computationally intensive kernel computation portion of the training algorithm. In addition to the kernel computation, the inference phase of the SVM classifier is built into the IP core, and its use can be switched on the fly. The computational latency and memory bandwidth of an IP core are optimized using loop pipelining and DMA burst data transfer. With the help of hardware/software co-design, the IP core is integrated into the design of a flexible and re-usable System on Chip (SoC) called PYNQ Overlay. The experiments show that the overlay outperforms the embedded processor, multiple hardware SVM classifiers, and hardware accelerated Convolutional Neural Networks (CNN) in terms of real-time efficiency. The Overlay makes much less use of the resources available on the chip in comparison to the majority of the CNN accelerators. The overlay achieves an average classification accuracy that is only 1% lower than that of an ARM Cortex-A9 processor, according to experimental results on six datasets. Furthermore, it can increase training speed by an average of 31.82x and inference speed by an average of 31.74x. In addition, the proposed Overlay design achieves a 2.3x improvement in average training speed, as measured in Mega bits per second, compared to existing SVM training implementations, along with incremental learning and multi-class classification support.

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

The security of Internet of Things (IoTs) devices in recent years has created interest in developing implementations of lightweight cryptographic algorithms for such systems. Additionally, open-source hardware and field-programable gate arrays (FPGAs) are gaining traction via newly developed tools, frameworks, and HDLs. This enables new methods of creating hardware and systems faster, more simply, and more efficiently. In this paper, the implementation of a system-on-chip (SoC) based on a 32-bit RISC-V processor with lightweight cryptographic accelerator cores in FPGA and an open-source integrating framework is presented. The system consists of a 32-bit VexRiscv processor, written in SpinalHDL, and lightweight cryptographic accelerator cores for the PRINCE block cipher, the PRESENT-80 block cipher, the ChaCha stream cipher, and the SHA3-512 hash function, written in Verilog HDL and optimized for low latency with fewer clock cycles. The primary aim of this work was to develop a customized SoC platform with a register-controlled bus suitable for integrating lightweight cryptographic cores to become compact embedded systems that require encryption functionalities. Additionally, custom firmware was developed to verify the functionality of the SoC with all integrated accelerator cores, and to evaluate the speed of cryptographic processing. The proposed system was successfully implemented in a Xilinx Nexys4 DDR FPGA development board. The resources of the system in the FPGA were low with 11,830 LUTs and 9552 FFs. The proposed system can be applicable to enhancing the security of Internet of Things systems.

A 7T high stable and low power SRAM cell design using QG-SNS FinFET

System on Chip (SoC) low power cache memories are in great demand. This requires novel devices like FinFET instead of MOSFET. FinFET comes out as a multi-gate, non-planar device which controls the short channel effects, power dissipation and leakage current. 7T SRAM cell designed using the Quad Gate Stacked Nano-sheets (QG-SNS) FinFET device has been presented. The simulation methodology and the performance parameters of QG-SNS FinFET device have also been discussed. The device shows better ON current, reduced leakage current and improved subthreshold slope. The performance of the 7T SRAM cell designed using QG-SNS FinFET (7T_SNS) for read-write operation has been analyzed in regard to leakage power, propagation delay and stability. This work compares the performance of 7T_SNS SRAM cell with other SRAM cells at nano-scaled technologies. The 7T_SNS SRAM cell achieves 370% better read stability compared to 6T CMOS cell. Write static noise margin of 7T_SNS cell is almost like 6T CMOS SRAM. The leakage power and read power of 7T_SNS cell is 99.99% better as compared to 6T CMOS SRAM. Therefore, a 7T_SNS SRAM cell design having minimum power utilization and better read stability is discussed in this paper.

The Development of a Cost-Effective Imaging Device Based on Thermographic Technology

Thermal vision-based devices are nowadays used in a number of industries, ranging from the automotive industry, surveillance, navigation, fire detection, and rescue missions to precision agriculture. This work describes the development of a low-cost imaging device based on thermographic technology. The proposed device uses a miniature microbolometer module, a 32-bit ARM microcontroller, and a high-accuracy ambient temperature sensor. The developed device is capable of enhancing RAW high dynamic thermal readings obtained from the sensor using a computationally efficient image enhancement algorithm and presenting its visual result on the integrated OLED display. The choice of microcontroller, rather than the alternative System on Chip (SoC), offers almost instantaneous power uptime and extremely low power consumption while providing real-time imaging of an environment. The implemented image enhancement algorithm employs the modified histogram equalization, where the ambient temperature sensor helps the algorithm enhance both background objects near ambient temperature and foreground objects (humans, animals, and other heat sources) that actively emit heat. The proposed imaging device was evaluated on a number of environmental scenarios using standard no-reference image quality measures and comparisons against the existing state-of-the-art enhancement algorithms. Qualitative results obtained from the survey of 11 subjects are also provided. The quantitative evaluations show that, on average, images acquired by the developed camera provide better perception quality in 75% of tested cases. According to qualitative evaluations, images acquired by the developed camera provide better perception quality in 69% of tested cases. The obtained results verify the usability of the developed low-cost device for a range of applications where thermal imaging is needed.

ArduSiPM technology: Compact and light All-in-one detectors for space application

ArduSiPM technology integrates System on Chip (SoC) innovation and Silicon photomultiplier (SiPM) detector improvements into a new generation of all-in-one scintillation detectors, developed by INFN Rome since 2014. To minimize reliance on pre-built Commercial off-the-shelf (COTS) components, we utilize the peripherals and CPU of the SoC for edge computing tasks and various functions, such as Counters, Analog-to-Digital Converters (ADCs), Digital-to-Analog Converters (DACs), Pulse-Width modulation (PWM), and digital input/output interfaces. Our compact electronic system eliminates the need for external data acquisition systems and ASICs, while also enabling the CPU to perform edge computing functions. The detector, capable of measuring the rate, arrival time (with a resolution of 7 ns correlated to the SoC main clock), and number of photons arriving on the SiPM, is ideal for radiation monitoring and highly sensitive photon detection. The INFN MICRO experiment explores circuits and engineering solutions for developing detectors for diverse fields such as Transient Luminous Events, analytical chemistry, and nano/picosatellites. Our ultimate goal is to integrate the detector into the onboard computer of a satellite, akin to navigation instruments and attitude control systems, with future improvements in SoC technology easily leveraged thanks to our approach’s independence from the specific SoC.

Miniaturized Wirelessly Powered and Controlled Implants for Multisite Stimulation.

This paper presents a miniaturized implant with a diameter of only 14 mm, which houses a novel System on Chip (SoC) enabling two voltage level stimulation of up to 16 implants using a single Tx coil. Each implant can operate at a distance of 80 mm in the air through the inductive resonant link. The SoC consumes only 27 μW static power and enables two channels with stimulation amplitudes of 1.8 V and 3.3 V and timing resolution of 100 μs. The SoC is implemented in the standard 180 nm complementary metal oxide semiconductor (CMOS) technology and has an area of 0.75 mm × 1.6 mm. The SoC comprises an RF rectifier, low drop-out regulator (LDO), error detection block, clock data recovery, finite state machine (FSM), and output stage. Each implant has a PCB-defined passcode, which enables the individual addressability of the implants for synchronized therapies. The implantable device weighs only 80 mg and sizes 20.1 mm3. Tolerance of up to 70° to angular misalignment was measured at a distance of 50 mm. The efficacy of bilateral stimulation was further verified by implanting two devices on two sides of a pig's neck and performing bilateral vagus nerve stimulation (VNS), while monitoring the heart rate.

RTL Implementation of AMBA AHB Protocol using Verilog

Abstract: The enactment of a computer system heavily depends on the design of its bus interconnect. A poorly designed system bus can hinder the transmission of instructions and data between the processor and memory or between peripheral devices and memory. To address these challenges, the Advanced Microcontroller Bus Architecture (AMBA) provides an open standard for connecting and managing functional blocks in a System-on-Chip (SoC). This architecture allows for developing multi-processor designs with many controllers and peripherals while ensuring the system is designed correctly the first time. Furthermore, the AMBA specifications are royalty-free and platform-independent. They can be used with any processor architecture. The project will provide an RTL view and an extracted design summary of the AMBA AHB module at the system-on-chip level. The AMBA High-performance Bus (AHB) is another part of the AMBA family of conventions. The AHB is designed to support highperformance, high-clock system modules and serves as the system's high-performance backbone bus. The AHB enables the efficient connection of low-power peripheral functions to processors, on-chip memories, and external off-chip memory interfaces. All signal transitions in the AHB relate only to the rising clock edge, allowing AHB peripherals to be easily integrated into any design flow. The project also describes the AMBA AHB design and implementation using Verilog, with read/write operations implemented using the Xilinx simulator.