System-on-chip Research Articles

Seizure-Cluster-Inception CNN (SciCNN): A Patient-Independent Epilepsy Tracking SoC With 0-Shot-Retraining.

Epilepsy tracking System-on-Chips (SoC) usually perform patient-specific classification to deal with the patient-to-patient seizure pattern variation from a surface electroencephalogram (EEG). However, the patient-specific classifier training requires the EEG signals from the target patients a priori, which involves costly and time-consuming hospitalization for the inpatient data collection. To address this issue, this paper presents a patient-independent epilepsy tracking SoC that is trained with pre-existing databases and can be directly deployed to the target patients without collecting their data and performing cumbersome patient-specific training beforehand. The proposed SoC adopts a Seizure-Cluster-Inception Convolutional Neural Network (SciCNN) Neural Processor (SNP) to reduce SRAM access rate by 179.05× with the Kernel-Wise Pipeline (KWP). The 22-Ch. SoC achieves event-based sensitivity of 90.3%/90.4%/83.3% and specificity of 93.6%/95.7%/88.6% on unseen patients from CHB-MIT database/EU database/local hospital patient, respectively.

Comparative analysis of meta heuristics algorithm for differential amplifier design

The design of analog circuits is very essential for the development of system design based on electronics as the world is analog in nature. Furthermore, performance of emerging products depends on analog circuits for reduction of power dissipation and improvement of speed. Though in the system on chip (SoC) analog circuit consumes less, it is more complex to design it due to the analog circuit nature complexity. The job of the evolutionary algorithm (EA) in the process of optimization of an analog circuit based on complementary metal oxide semiconductor (CMOS) is to get the appropriate values that can be used for the design parameters of the given circuit in such a way such that all the targeted specification of the given circuit can be obtained. The chaotic serial particle swarm optimization (CSPSO) and cuckoo search (CS) algorithms are lower than to those found through the particle swarm optimization (PSO) and differential evolution (DE) algorithms. The CS algorithm obtained all the desired specifications with less power dissipation and the least total transistor area compared to those attained by the DE and PSO algorithms.

2D router chip design, analysis, and simulation for effective communication

<p class="Correspondencedetails"><span lang="EN-US">The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.</span></p>

Acceleration of convolutional neural network based diabetic retinopathy diagnosis system on field programmable gate array

Diabetic retinopathy (DR) is one of the most common causes of blindness. The necessity for a robust and automated DR screening system for regular examination has long been recognized in order to identify DR at an early stage. In this paper, an embedded DR diagnosis system based on convolutional neural networks (CNNs) has been proposed to assess the proper stage of DR. We coupled the power of CNN with transfer learning to design our model based on state-of-the-art architecture. We preprocessed the input data, which is color fundus photography, to reduce undesirable noise in the image. After training many models on the dataset, we chose the adopted ResNet50 because it produced the best results, with a 92.90% accuracy. Extensive experiments and comparisons with other research work show that the proposed method is effective. Furthermore, the CNN model has been implemented on an embedded target to be a part of a medical instrument diagnostic system. We have accelerated our model inference on a field programmable gate array (FPGA) using Xilinx tools. Results have confirmed that a customized FPGA system on chip (SoC) with hardware accelerators is a promising target for our DR detection model with high performance and low power consumption.

Defense Against On-Chip Trojans Enabling Traffic Analysis Attacks Based on Machine Learning and Data Augmentation

Modern computing systems involve huge data exchange across various sections of the processing system. To facilitate this, Network-on-Chip (NoC) serve as a crucial infrastructure that connect the processing cores to memory, peripherals, etc. The system could be put at great risk should the NoC system become compromised. The NoCs are used in multi/many-core processors; this domain is experiencing increased threats because of Hardware Trojan (HT) embedded in the multi core processing systems due to the presence of third-party entities in the system-on-chip (SoC) design pipeline. Protecting user and system level privacy becomes important in such multi core systems to enable trust. By embedding a hardware Trojan (HT) in a NoC, the adversary can snoop on important insights regarding the applications executing on the system or the user profile information. An attack of such calibre can compromise privacy thereby enabling more advanced attack on the entire system. This work demonstrates the capability of a traffic analysis attack when a few HTs are embedded in the NoC switches of a multi/many-core processor. The attack is capable of exposing sensitive information to an external malicious attacker who can then analyze the payload data with sophisticated machine learning (ML) techniques to infer the applications executing on the system. We also evaluate the performance of a generative adversarial network (GAN) strengthened attacker model that offers more robustness for data paucity scenarios. We propose a Simulated Annealing-based randomized routing algorithm based defense for NoCs thus thwarting the attack. The results demonstrate that the proposed randomized routing algorithm could reduce the accuracy of identifying user profiles by the attacker from >98% to <15% in multi/many-core systems.

DEMAP: differential evolution mapping for network on chip optimization

Network-on-chip (NoC) is a new paradigm for system-on-chip (SoC) design, which facilitates the interconnection and integration of complex components. Since this technology is still new, significant research efforts are needed to accelerate and simplify the design phases. Mapping is a critical phase in the NoC design process, as a mismatch of application software components can significantly impact the final system's performance. Therefore, it is essential to develop automated tools and methods to ensure this step. The main objective of this project is to develop a new approach that can be used to map applications on the NoC architecture to reduce communication costs. To achieve this goal, we have opted for an optimization algorithm, specifically the differential evolution algorithm.

Enabling Co-Design of 3D Heterogeneous Packages

The days of ‘throwing it over the wall’ are over. Heterogeneous Integration (HI) is ushering in a new era of electronic product design with collaboration at its core – one that lives or dies on seamless interaction between analog/digital IC teams and package design teams. The use of advanced packaging technologies to combine smaller, discrete chiplets into one system-in-package (SiP) not only pushes the need for more advanced multi-die packaging, it makes packaging part and parcel of the process. And in doing so, it significantly reduces dependance on Moore’s Law at a time in which building an advanced monolithic system-on-chip (SoC) has become prohibitively expensive. For many tech companies, Moore’s Law no longer represents the best technical nor economical path to designing a product. And for a great many of those companies, HI presents a solution – SiPs close to the SoC form factor but with far lower overall cost, greater yield and perhaps most importantly, faster time to market. While SiP as a packaging concept has been around for decades, the recent tsunami of designs that have adopted HI is truly a disruptive change. This presentation will outline some potential solutions to the challenges design teams face when pivoting from monolithic IC design to 3D heterogenous package design.

Universal Chiplet Interconnect Express Г (UCIeГ)

Align Industry around an open platform to enable chiplet based solutions. Enables construction of SoCs that exceed maximum reticle size -Package becomes new System-on-a-Chip (SoC) with same dies (Scale Up) -Reduces time-to-solution (e.g., enables die reuse) -Lowers portfolio cost (product &amp; project) -Enables optimal process technologies -Smaller (better yield) -Reduces IP porting costs -Lowers product SKU cost -Enables a customizable, standard-based product for specific use cases (bespoke solutions) -Scales innovation (manufacturing and process locked IPs)

Mask-less Laser Direct Imaging &amp; Adaptive Patterning for Fan-Out Heterogeneous Integration

Mask-less Laser Direct Imaging &amp; Adaptive Patterning for Fan-Out Heterogeneous Integration

FSMx-Ultra: Finite State Machine Extraction From Gate-Level Netlist for Security Assessment

Numerous security vulnerability assessment techniques urge precise and fast finite state machines (FSMs) extraction from the design under evaluation. Sequential logic locking, watermark insertion, fault-injection assessment of a System-on-a-Chip (SoC) control flow, information leakage assessment, and reverse engineering at gate-level abstraction, to name a few, require precise FSM extraction from the synthesized netlist of the design. Unfortunately, no reliable solutions are currently available for fast and accurate extraction of FSMs from the highly unstructured gate-level netlist for effective security evaluation. The major challenge in developing such a solution is precise recognition of FSM state flip-flops in a netlist having a massive collection of flip-flops. In this paper, we propose FSMx-Ultra, a framework for extracting FSMs from extremely unstructured gate-level netlists. FSMx-Ultra utilizes state-of-the-art graph theory concepts and algorithms to distinguish FSM state registers from other registers and then constructs gate-level state transition graphs (STGs) for each identified FSM state register using automatic test pattern generation (ATPG) techniques. The results of our experiments on 14 open-source benchmark designs illustrate that FSMx-Ultra can recover all FSMs quickly and precisely from synthesized gate-level netlists of diverse complexity and size utilizing various state encoding schemes.

Versatile On-Chip Programming of Circuit Hardware for Wearable and Implantable Biomedical Microdevices.

Wearable and implantable microscale electronic sensors have been developed for a range of biomedical applications. The sensors, typically millimeter size silicon microchips, are sought for multiple sensing functions but are severely constrained by size and power. To address these challenges, a hardware programmable application-specific integrated circuit design is proposed and post-process methodology is exemplified by the design of battery-less wireless microchips. Specifically, both mixed-signal and radio frequency circuits are designed by incorporating metal fuses and anti-fuses on the top metal layer to enable programmability of any number of features in hardware of the system-on-chip (SoC) designs. This is accomplished in post-foundry editing by combining laser ablation and focused ion beam processing. The programmability provided by the technique can significantly accelerate the SoC chip development process by enabling the exploration of multiple internal circuit parameters without the requirement of additional programming pads or extra power consumption. As examples, experimental results are described for sub-millimeter size complementary metal-oxide-semiconductor microchips being developed for wireless electroencephalogram sensors and as implantable microstimulators for neural interfaces. The editing technique can be broadly applicable for miniaturized biomedical wearables and implants, opening up new possibilities for their expedited development and adoption in the field of smart healthcare.

Research of the system-on-chip-based relay protection technology

The relay protection device is the core equipment that ensures the safe and stable operation of a power grid. With the open access of a large number of distributed generation, DC transmission and electric vehicles, a new deep low-carbon power system dominated by power electronic devices has gradually been formed. It is difficult for the traditional control and protection architecture, methods, and technology to meet the business characteristics and functional requirements of a diversified interaction, agile response, safety, and credibility of the power grid in the future. This paper presents a chip-based relay protection technology based on system-on-chip (SoC), which is described from four aspects, namely, the architectural design of the relay protection SoC, software and hardware cooperative relay protection based on the SoC IP core, experimental verification, and engineering application. The results show that the relay protection SoC proposed in this paper has significantly improved the performance of high-speed data acquisition and interaction through hardware algorithm engine acceleration and software and hardware collaborative computing, which is helpful to realize the local equipment operation and the integration of primary and secondary equipment, shorten the protection action time, and improve the speed, reliability, and stability of relay protection devices.

Bulk-Switching Memristor-Based Compute-In-Memory Module for Deep Neural Network Training.

The constant drive to achieve higher performance in deep neural networks (DNNs) has led to the proliferation of very large models. Model training, however, requires intensive computation time and energy. Memristor-based compute-in-memory (CIM) modules can perform vector-matrix multiplication (VMM) in place and in parallel, and have shown great promises in DNN inference applications. However, CIM-based model training faces challenges due to non-linear weight updates, device variations, and low-precision. In this work, a mixed-precision training scheme is experimentally implemented to mitigate these effects using a bulk-switching memristor-based CIM module. Low-precision CIM modules are used to accelerate the expensive VMM operations, with high-precision weight updates accumulated in digital units. Memristor devices are only changed when the accumulated weight update value exceeds a pre-defined threshold. The proposed scheme is implemented with a system-onchip of fully integrated analog CIM modules and digital sub-systems, showing fast convergence of LeNet training to 97.73%. The efficacy of training larger models is evaluated using realistic hardware parameters and verifies that CIM modules can enable efficient mix-precision DNN training with accuracy comparable to full-precision software-trained models. Additionally, models trained on chip are inherently robust to hardware variations, allowing direct mapping to CIM inference chips without additional re-training.

On-Machine CIS SoC-Based Layerwise Inspection System for MEX Additive Manufacturing

Additive manufacturing processes build three-dimensional objects usually following a layer-upon-layer strategy. An interesting feature of this strategy is that each layer could be inspected before the next one is deposited. On-machine integration of layerwise inspection systems would not only allow for early characterization of the dimensional and geometric quality of the part, but also for the detection of intralayer defects. Contact image sensors (CIS), such as those used in desktop flatbed scanners, could be used for this purpose since they would provide bi-dimensional digital images of the whole layer and its neighborhood. CIS images combine high resolutions with a reduced acquisition time. In this work, a material extrusion (MEX) additive manufacturing system, with layerwise inspection capabilities is proposed. The system has been equipped with the CIS that Epson uses in its Perfection V39 flatbed scanner. The sensor provides two analog output signals, each one consisting on 2584 voltage levels, that represent the amount of light reflected by the material. This analog information is sent to a parallel AD converter, where an 8-bit encoding is assigned to each one of the pixels on the digitized image. To overcome microcontroller-related problems, a Zynq®-7000 system-on-chip (SoC) has been used. This SoC integrates an ARM® based processor, with the hardware programming of a field programmable gate array (FPGA). This architecture ensures an accurate and controlled readout of the various AD converters. The resultant digital image of each layer could then be then processed using different algorithms to detect defects, extract the geometry of the layer contour and characterize the dimensional and geometric quality of the object. In the example provided, a forced error consisting on 0.2 mm height local deviations, caused by a variation in extrusion temperature, was identified from 2D grayscale images obtained with the CIS sensor.

Design and implementation of low-power, high-speed, reliable and secured Hardware Accelerator using 28 nm technology for biomedical devices

This paper implements a Hardware Accelerator (HA) for Wireless Body Sensor Networks (WBSNs) using 28 nm technology on Zynq system-on-a-chip (SOC) using Vivado and VITIS high-level synthesis tool. The Vitis integrated development environment (IDE) is a software-only development environment that Integrates with other Xilinx tools. The Zynq® SoC combines a state-of-the-art processor system (PS) and programmable logic (PL) into a single cohesive device. WBSNs contain different processing techniques like predictor, compressor, encryption encoder, and Error Control Coding (ECC) before transmission. These techniques are implemented and validated using the Xilinx® Software Development Kit (SDK) tool along with the PYNQ Z2 board having Zynq SOC respectively. Similarly, the processing techniques are implemented on PS block as HA. The results of the work show the data collection and processing through the dual-core ARM Cortex A9 processor of the board. The purpose of the work is to calculate the time required to process the bio-signals through the controller solely and using HA. The proposed work, mainly WBSN using HA shows an improvement of 81% in the speed compared with existing methods. Further, results of the synthesis and implementation strategy show improvement in power and area of HA with WBSN.

Design and Analysis of Four Port Router for Network-On-Chip Applications

System-On-Chip (SoC) is a popular VLSI technology that integrates multiple devices onto a single chip. The Network-On-Chip (NOC) concept, which is a novel paradigm in sophisticated System-On-Chip designs that offers efficient communication throughout the on-chip networks, is used to communicate amongst various devices. The router is the main component in an NoC architecture that is responsible for routing information. Packets are sent through a network by an NoC made up of routers. A routing algorithm divides packets into flow control digits (flits) and determines their paths. The placement of routers is determined by the network topology. In the present work, the main target is to design and analyse the router, which is primarily based on a number of critical factors, including topology, routing algorithm, and packet format. The performance of the suggested router is evaluated and compared to that of the Conventional Wormhole Router (CWHR) with respect to power and slack time (ST). When compared to a traditional wormhole router, the proposed router architecture has 18% less slack. As a result, total power consumption is reduced by 29.3% as compared to traditional wormhole architecture. The architecture is synthesized using Cadence Encounter RTL Compiler using standard 65nm technology.

A 4.5 μW Miniaturized 3-Channel Wireless Intra-Cardiac Acquisition System.

This article presents a chip designed for wireless intra-cardiac monitoring systems. The design consists of a three-channel analog front-end, a pulse-width modulator featuring output-frequency offset and temperature calibration, and inductive data telemetry. By employing a resistance boosting technique in the instrumentation amplifier feedback, the pseudo-resistor exhibits lower non-linearity, leading to a total harmonic distortion of below 0.1%. Furthermore, the boosting technique enhances the feedback resistance, leading to a reduction in the size of the feedback capacitor and, consequently, the overall size. To make the modulator's output frequency resilient to temperature and process changes, coarse and fine-tuning algorithms are used. The front-end channel is capable of extracting the intra-cardiac signal with an effective number of bits of 8.9, while exhibiting an input-referred noise of less than 2.7 μVrms, and consuming 200 nW per channel. The front-end output is encoded by an ASK-PWM modulator, which drives an on-chip transmitter at 13.56 MHz. The proposed System-on-Chip (SoC) is fabricated in a 0.18 μm standard CMOS technology and consumes 4.5 μW while occupying 1.125 mm2.

A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

A double-edge-triggered digital low dropout regulator (DLDO) is proposed with a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) for a system-on-chip (SoC) application. To achieve a fast transient response, the main comparator generates the comparison result at the rising edge of the AVC, and this result is sampled by the coarse or fine bidirectional shifter register at the falling edge of the AVC. Furthermore, the clock frequency can be boosted from 8 MHz at the steady state to 50 MHz by the AVC when the output current suffers from a sudden change, and it can also be adjusted in real-time according to the output voltage, which avoids the oscillation phenomenon and decreases the power consumption during the recovery process. To further lower the power consumption, the self-clock comparator replaces the conventional static comparator in the transient detector. The post-simulation results show that the proposed DLDO consumes a quiescent current of 95.13 μA in the steady state, and drives a maximum load current of 25 mA at the supply power of 0.6 V with an active area of 0.053-mm2 in a 180 nm CMOS process. When the load current jumps from 0.5 mA to 25 mA at the edge of 100 ps, the undershoot voltage and overshoot voltage are only 335 mV with the recovery time of 2.7 μs and 47.6 mV with the recovery time of 2.1 μs at the total on-chip capacitor of 50 pF, respectively, resulting in two competitive figures of merits (FoMs) than the previous works.

Advancements in Spaceborne Synthetic Aperture Radar Imaging with System-on-Chip Architecture and System Fault-Tolerant Technology

With the continuous development of satellite payload and system-on-chip (SoC) technology, spaceborne real-time synthetic aperture radar (SAR) imaging systems play a crucial role in various defense and civilian domains, including Earth remote sensing, military reconnaissance, disaster mitigation, and resource exploration. However, designing high-performance and high-reliability SAR imaging systems that operate in harsh environmental conditions while adhering to strict size, weight, and power consumption constraints remains a significant challenge. In this paper, we introduce a spaceborne SAR imaging chip based on a SoC architecture with system fault-tolerant technology. The fault-tolerant SAR SoC architecture has a CPU, interface subsystem, memory subsystem, data transit subsystem, and data processing subsystem. The data processing subsystem, which includes fast Fourier transform (FFT) modules, coordinated rotation digital computer (CORDIC) modules (for phase factor calculation), and complex multiplication modules, is the most critical component and can achieve various modes of SAR imaging. Through analyzing the computational requirements of various modes of SAR, we found that FFT accounted for over 50% of the total computational workload in SAR imaging processing, while the CORDIC modules for phase factor generation accounted for around 30%. Therefore, ensuring the fault tolerance of these two modules is crucial. To address this issue, we propose a word-length optimization redundancy (WLOR) method to make the fixed-point pipelined FFT processors in FFT modules fault tolerant. Additionally, we propose a fault-tolerant pipeline CORDIC architecture utilizing error correction code (ECC) and sum of squares (SOS) check. For other parts of the SoC architecture, we propose a generic partial triple modular redundancy (TMR) hardening method based on the HITS algorithm to improve fault tolerance. Finally, we developed a fully automated FPGA-based fault injection platform to test the design’s effectiveness by injecting errors at arbitrary locations. The simulation results demonstrate that the proposed methods significantly improved the chip’s fault tolerance, making the SAR imaging chip safer and more reliable. We also implemented a prototype measurement system with a chip-included board and demonstrated the proposed design’s performance on the Chinese Gaofen-3 strip-map continuous imaging system. The chip requires 9.2 s, 50.6 s, and 7.4 s for a strip-map with 16,384 × 16,384 granularity, multi-channel strip-map with 65,536 × 8192 granularity, and multi-channel scan mode with 32,768 × 4096 granularity, respectively, and the system hardware consumes 6.9 W of power to process the SAR raw data.

A Review Paper on Multi-tasking on Network on Chip(NOC)

Now a days development of Integrated Circuit technology is composed of multiple cores in a single chip called System on Chip (SoC). The technology has advanced from to single to multi core so as to improve the performance. These require effective communication, High performance, flexibility, scalability and design friendly interconnection. Before the initiation of Network on Chip (NoC), interconnection is based on wire and they cannot encounter ever increasing demand for on chip systems due to lack of scalability. NoC has several advantages such as high bandwidth, low power consumption and scalability. The interconnection among multiple cores on a chip have impact on communication and performance of chip design in terms of collision occurrence, noise, and pocket loss ratio and delay. Therefore, it is valuable studying the different multitasking algorithms. This paper reviews the widespread NoC algorithms and also few recent inclinations in interconnection networks. The area, power consumption, design complexity and congestion are studied to review the performance and summarize their merits.