System-on-chip Research Articles

Cosmo ArduSiPM: An All-in-One Scintillation-Based Particle Detector for Earth and Space Application.

Thanks to advancements in silicon photomultiplier sensors (SiPMs) and system-on-chip (SoC) technology, our INFN Roma1 group developed ArduSiPM in 2012, the first all-in-one scintillator particle detector in the literature. It used a custom Arduino Due shield to process fast signals, utilizing the Microchip Sam3X8E SoC's internal peripherals to control and acquire SiPM signals. The availability of radiation-tolerant SoCs, combined with the goal of reducing system space and weight, led to the development of an innovative second-generation board, a better-performing device called Cosmo ArduSiPM, suitable for space missions. The architecture of the new detector is based on the Microchip SAMV71 300 MHz, 32-bit ARM® Cortex®-M7 (Microchip Technology Inc., Chandler, AZ, USA). While the analog front-end is essentially identical to the ArduSiPM, it utilizes components with the smallest possible package. The board fits in a CubeSat module. Thanks to the compact design, the board has two independent channels, with a total weight of only 40 grams within a CubeSat form factor. The ArduSiPM architecture is based on a single microcontroller and fast discrete analog electronics. It benefits from the continued development of SoCs related to the IoT (Internet of Things) market. Compared with a system with a custom ASIC, this architecture based on software and SoC capabilities offers considerable advantages in terms of cost and development time. The ability to incorporate new commercial SoCs, continuously emerging from advancements in the aerospace and automotive industries, provides the system with a robust foundation for sustained growth over the years. A detailed characterization of the hardware and the system's response to different photon fluxes is presented in this article. Additionally, coupling the device with a scintillator was tested at the end of this article as a preliminary trial for future measurements, showing potential for further enhancement of the detector's capabilities.

Secure hardware IP of GLRT cascade using color interval graph based embedded fingerprint for ECG detector

This paper presents a security aware design methodology to design secure generalized likelihood ratio test (GLRT) hardware intellectual property (IP) core for electrocardiogram (ECG) detector against IP piracy and fraudulent claim of IP ownership threats. Integrating authentic (secure version) GLRT hardware IP core in the system-on-chip (SoC) of ECG detectors is paramount for reliable operation and estimation of ECG parametric data, such as Q wave, R wave and S wave (QRS) complex detection. A pirated GLRT hardware IP integrated into an ECG detector may result in an unreliable/erratic estimation of ECG parametric data that can be hazardous and fatal for the end patient. The proposed methodology presents an integrated design flow to secure micro GLRT and GLRT cascade hardware IP cores for the ECG detector, using the colored interval graph (CIG) framework based fingerprint biometric, during high level synthesis (HLS). The proposed approach integrates a fingerprint biometric based security constraint generation process for securing the GLRT hardware IP core. This paper also presents a secure register transfer level (RTL) datapath design corresponding to micro GLRT and GLRT cascade hardware IP cores with embedded IP vendor's fingerprint. The proposed secure GLRT hardware IP core embedded with fingerprint biometric achieves superior results in terms of probability of coincidence and tamper tolerance than other security approaches. More explicitly, the proposed approach reports a significantly lower value of probability of coincidence and stronger value for tamper tolerance. Further, the proposed approach incurs zero design cost overhead.

SoC-FPGA Based Concept of Hardware Aided Quantum Simulation

Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of standard systems are reaching the limits of physics known to humankind. Fast, programmable systems with relatively low power consumption are a different concept for performing complex calculations. Highly parallel processing opens up a number of possibilities in the context of accelerating calculations. Application of SoC (System On Chip) with FPGA (Field-Programmable Gate Array) enables to delegate of a part of computations to the gates matrix, thereby expediting processing by using parallelization of hardware operations. This paper presents the general concept of using SoC FPGA systems to support CPU (Central Processing Unit) in many modern tasks. While some tasks might be really hard to implement on an FPGA in a reasonable time, the SoC FPGA platform allows for easy low-level interconnections, and with such virtualized access to the hardware computing resources, it is seen as making FPGAs, or hardware in general, more accessible to engineers accustomed to high-level solutions. The concept presented in the article takes into account the limited resources of cheaper educational platforms, which, however, still provide an interesting and alternative hybrid solution to the problem of parallelization and acceleration of data processing. This allows to overcome encountered limitations and maintain the flexibility known from high-level solutions and high performance achieved with low-level programming, without the need for a high financial background.

A Cell-Type Selective Stimulation and Recording System for Retinal Ganglion Cells.

Future retinal implants will require a stimulation selectivity between different sub-types of Retinal Ganglion Cells (RGCs) to evoke natural perceptions rather than phosphenes in patients. To achieve this, a cell-type specific stimulation pipeline is required that identifies target RGC sub-types from recorded input images and extracts the specific stimulation parameters to activate this cell-type selectively. Promising biological experiments showed that ON-/OFF- sustained/transient RGCs could be selectively activated by modulating repetition rate and amplitude of an electrical stimulation current in the kilohertz range. This research presents a 42 channel current controlled stimulation and recording system on chip (SoC) with parameter input from a real time target RGC selection algorithm. The SoC is able to stimulate retinal tissue with sinusoidal frequencies higher than 1 kHz at amplitudes of up to 200 μA at a supply voltage of 1.8 V. It also includes tunable recording units with an integrated action potential detection pipeline that are able to amplify signals between 1 Hz and 50 kHz. The required area of one stimulator is 0.0071 mm2, while one recording unit consumes an area of 0.0092 mm2. The application of sinusoidal stimulation currents in the kilohertz range towards retinal tissue leads to a suppressive response of only certain RGC sub-types that has not been oberved before, using electrical stimulation. Because this response is very similar to the natural light response of RGCs, this stimulation approach can lead to a more genuine visual perception for patients using retinal implants.

Single event effects evaluation on convolution neural network in Xilinx 28 nm system on chip

Abstract Convolutional neural networks (CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic particles, such as heavy ions, protons, and alpha particles, can induce single event effects (SEEs) that lead CNNs to malfunction and can significantly impact the reliability of a CNN system. In this paper, the MNIST CNN system was constructed based on a 28 nm system-on-chip (SoC), and then an alpha particle irradiation experiment and fault injection were applied to evaluate the SEE of the CNN system. Various types of soft errors in the CNN system have been detected, and the SEE cross sections have been calculated. Furthermore, the mechanisms behind some soft errors have been explained. This research will provide technical support for the design of radiation-resistant artificial intelligence chips.

AIfES: A Next-Generation Edge AI Framework.

Edge Artificial Intelligence (AI) relies on the integration of Machine Learning (ML) into even the smallest embedded devices, thus enabling local intelligence in real-world applications, e.g. for image or speech processing. Traditional Edge AI frameworks lack important aspects required to keep up with recent and upcoming ML innovations. These aspects include low flexibility concerning the target hardware and limited support for custom hardware accelerator integration. Artificial Intelligence for Embedded Systems Framework (AIfES) has the goal to overcome these challenges faced by traditional edge AI frameworks. In this paper, we give a detailed overview of the architecture of AIfES and the applied design principles. Finally, we compare AIfES with TensorFlow Lite for Microcontrollers (TFLM) on an ARM Cortex-M4-based System-on-Chip (SoC) using fully connected neural networks (FCNNs) and convolutional neural networks (CNNs). AIfES outperforms TFLM in both execution time and memory consumption for the FCNNs. Additionally, using AIfES reduces memory consumption by up to 54% when using CNNs. Furthermore, we show the performance of AIfES during the training of FCNN as well as CNN and demonstrate the feasibility of training a CNN on a resource-constrained device with a memory usage of slightly more than 100 kB of RAM.

Fully Automatic Solar Grass cutter

Abstract: "The term 'Embedded' signifies the integration of multiple independent devices into a single chip, commonly referred to as a System on Chip (SoC). The advent of VLSI technology has enabled the creation of high-speed, cost-effective, low-power, and co impact integrated circuits. The microcontroller employed for these applications is often referred to as an IBP (Itty Bitty Processor) or an embedded processor. "Multi-task oriented systems may introduce time delays, which can be inefficient in certain applications. In such scenarios, microcontrollers play a crucial role in embedded system design. In this context, we have developed a versatile embedded system application titled 'PC-controlled pick and place Robot.' This project serves as a demonstration of the effective utilization of automation and is structured around the integration of a microcontroller and a personal computer (PC). "The objective of our project is to manage the robot using commands transmitted via Zigbee protocol communication from a personal computer. These commands include F (forward), B (backward), L (left), R (right)

MILITARY-EYES: A Real-Time Hyper-Tuned and Optimised Object Detection Approach Tailored for Military Dataset

Accurately identifying all objects of interest inside the specified frame of reference is crucial for object identification techniques to allow machine vision to interpret images successfully. Theoretical frameworks from computer vision and deep learning have informed many potential solutions to this problem. However, current approaches frequently fail when faced with objects going through random geometric changes and continually show shortcomings when identifying small, dense objects. This research looks at state-of-the-art object detection methods, compares them, and then suggests a convolutional object detection network that has been tweaked to fix the problems with the existing methods. Comparing our research to existing approaches, we find that they perform better. We accomplish this by training deep convolutional networks to detect geometric transformations and adjusting the networks to handle multi-scaled features. The results achieved after the optimization of the You only look once (YOLO) V5 & V7 are stated in this paper. The experiments demonstrated that YOLO v8 achieved higher accuracy than the hyper-tuned YOLO V5 and V7, with an average Precision (mAP) score of 52.8% on the customized military dataset running at 60 Frames Per Second (FPS). Object detection using deep neural networks (DNNs) poses a significant challenge due to the high computational and power requirements, mainly when deployed on general-purpose platforms such as CPUs and GPUs. However, addressing these limitations becomes crucial for efficient edge computing tasks like object detection, where faster, smaller, and energy-efficient solutions are essential. To overcome these challenges, system-on-chip (SoC) designs emerge as a promising solution.

An Energy-Efficient Field-Programmable Gate Array Rapid Implementation of a Structural Health Monitoring System

System health monitoring (SHM) of a ball screw laboratory system using an embedded real-time platform based on Field-Programmable Gate Array (FPGA) technology was developed. The ball screw condition assessment algorithms based on machine learning approaches implemented on multiple platforms were compared and evaluated. Studies on electric power consumption during the processing of the proposed structure of a neural network, implementing SHM, were carried out for three hardware platforms: computer, Raspberry Pi 4B, and Kria KV260. It was found that the average electrical power consumed during calculations is the lowest for the Kria platform using the FPGA system. However, the best ratio of the average power consumption to the accuracy of the neural network was obtained for the Raspberry Pi 4B. The concept of an efficient and energy-saving hardware platform that enables monitoring and analysis of the operation of the selected dynamic system was proposed. It allows for easy integration of many software environments (e.g., MATLAB and Python) with the System-on-a-Chip (SoC) platform containing an FPGA and a CPU.

Design and Modeling of a Terahertz Transceiver for Intra- and Inter-Chip Communications in Wireless Network-on-Chip Architectures.

This paper addresses the increasing demand for computing power and the challenges associated with adding more core units to a computer processor. It explores the utilization of System-on-Chip (SoC) technology, which integrates Terahertz (THz) wave communication capabilities for intra- and inter-chip communication, using the concept of Wireless Network-on-Chips (WNoCs). Various types of network topologies are discussed, along with the disadvantages of wired networks. We explore the idea of applying wireless connections among cores and across the chip. Additionally, we describe the WNoC architecture, the flip-chip package, and the THz antenna. Electromagnetic fields are analyzed using a full-wave simulation software, Ansys High Frequency Structure Simulator (HFSS). The simulation is conducted with dipole and zigzag antennas communicating within the chip at resonant frequencies of 446 GHz and 462.5 GHz, with transmission coefficients of around -28 dB and -33 to -41 dB, respectively. Transmission coefficient characterization, path loss analysis, a study of electric field distribution, and a basic link budget for transmission are provided. Furthermore, the feasibility of calculated transmission power is validated in cases of high insertion loss, ensuring that the achieved energy expenditure is less than 1 pJ/bit. Finally, employing a similar setup, we study intra-chip communication using the same antennas. Simulation results indicate that the zigzag antenna exhibits a higher electric field magnitude compared with the dipole antenna across the simulated chip structure. We conclude that transmission occurs through reflection from the ground plane of a printed circuit board (PCB), as evidenced by the electric field distribution.

Network on Chip and Its Low Power Techniques

The advent of Network-On-Chip (NoC) architecture has significantly revolutionized the design of complex System-On-Chip (SoC) systems by providing scalable and efficient communication infrastructures. NoC architectures offer advantages such as high bandwidth; low latency and better scalability compared with traditional bus-based communication architectures. However, the ever-increasing demand for higher performance and lower power consumption poses significant challenges for NoC designers. This article reviews the basic architectures and design issues of NoCs with SoCs and further extended with research challenges and low power techniques. Key Words: Network-On-Chip, System-On-Chip, latency and scalability

Low-Temperature Nanosecond Laser Process of HZO-IGZO FeFETs toward Monolithic 3D System on Chip Integration.

Ferroelectric field-effect transistors (FeFETs) are increasingly important for in-memory computing and monolithic 3D (M3D) integration in system-on-chip (SoC) applications. However, the high-temperature processing required by most ferroelectric memories can lead to thermal damage to the underlying device layers, which poses significant physical limitations for 3D integration processes. To solve this problem, the study proposes using a nanosecond pulsed laser for selective annealing of hafnia-based FeFETs, enabling precise control of heat penetration depth within thin films. Sufficient thermal energy is delivered to the IGZO oxide channel and HZO ferroelectric gate oxide without causing thermal damage to the bottom layer, which has a low transition temperature (<250 °C). Using optimized laser conditions, a fast response time (<1 µs) and excellent stability (cycle >106, retention >106 s) are achieved in the ferroelectric HZO film. The resulting FeFET exhibited a wide memory window (>1.7V) with a high on/off ratio (>105). In addition, moderate ferroelectric properties (2·Pr of 14.7 µCcm-2) and pattern recognition rate-based linearity (potentiation: 1.13, depression: 1.6) are obtained. These results demonstrate compatibility in HZO FeFETs by specific laser annealing control and thin-film layer design for various structures (3D integrated, flexible) with neuromorphic applications.

A Review on Design and Verification of Programmable UART with AXI

A Review on Design and Verification of Programmable UART with AXI

Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors.

The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter's own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of -3.3 V.

Energy-aware application mapping methods for mesh-based hybrid wireless network-on-chips

The 2D mesh topology-based Network-on-Chip (NoC) is a prevalent structure in System-on-Chip (SoC) designs, offering implementation and fabrication benefits. However, increased NoC scale leads to longer communication paths, more hops, and higher end-to-end latency and energy consumption. To mitigate these issues, Wireless NoC (WiNoC) integrates wireless communication, enhancing data rates, energy efficiency, and routing flexibility. Despite several mapping algorithms for NoCs, optimal techniques for hybrid WiNoCs are underexplored. This study proposes two novel application mapping methods for 2D mesh topology-based hybrid WiNoCs, using quadratic programming (QP) and simulated annealing (SA). Our goal is to minimize communication-related energy consumption. We evaluated these methods across various wireless router configurations, benchmarks, and custom application graphs. The QP-based method excels in smaller problems, while the SA-based approach yields optimal or near-optimal results for larger sizes within practical runtimes.

Research of the readout electronics for X-ray beam-position feedback system of SAPS

For 4th generation synchrotron radiation (SR) light sources, the X-ray beam-position stability is one of the crucial factors in cutting-edge experiments. Instead of traditional passive vibration isolation techniques, active vibration isolation measures based on feedback control technology have begun to play an important role for stabilizing the beam-position. The readout electronics of the feedback control system is presented in the paper. The proposed design is based on the integration of proportion integral differential (PID) controller and system on chip (SoC) module. By using the ARM for analyzing the convergence speed of PID controller with different parameters and configuring it, the readout electronics flexibly adapts to different vibration environments. The readout circuits based on this method is implemented for southern advanced photon source, and tests are carried out in the laboratory to evaluate the readout electronics. The results show that it can weaken the influence of vibration sources below 5Hz on the beam-position.

Universal 12-lead ECG representation for signal denoising and cardiovascular disease detection by fusing generative and contrastive learning

With the wide use of electrocardiogram (ECG) technology, more and more ECGs have been collected and stored. However, ECG labeling is costly and laborious, the utilization of unlabeled ECG is still a critical challenge. Self-supervised learning (SSL) is a way to deal with this problem, which can learn representations from unlabeled ECG and use them for downstream tasks. In this study, a novel SSL model that fuses generative learning (denoising autoencoder, DAE) and contrastive learning (CL) is proposed to learn robust representations from unlabeled ECG for downstream denoising and classification. The 12-lead ECGs are separated into one-dimensional single-lead ECGs and ECG-specific noises are added to the original ECGs as the data augmentation method. To improve the model's denoising and feature extraction abilities, the reconstruction loss and contrastive loss are combined during the pretraining phase. In the downstream classification task, a multi-branch network is used to enhance the correlation between different ECG leads. As a result, it improves the denoising performance over the standard DAE by an average of 5.20%. In the classification tasks for the Chapman, PTB-XL, and CPSC2018 databases, compared to existing work, the accuracies in linear probe are increased by at least 2.49%, 1.09%, and 2.61%, respectively. In addition, an SoC (system-on-a-chip) based heterogeneous deployment scheme is designed. It is 13.69–14.26 times faster in inference than pure software deployment and enables real-time detection of ECG signals. The proposed method provides a good way to utilize unlabeled ECG, and the designed deployment scheme has great potential for medical applications.

A Low-Noise Low-Power 0.001Hz-1kHz Neural Recording System-on-Chip With Sample-Level Duty-Cycling.

Advances in brain-machine interfaces and wearable biomedical sensors for healthcare and human-computer interactions call for precision electrophysiology to resolve a variety of biopotential signals across the body that cover a wide range of frequencies, from the mHz-range electrogastrogram (EGG) to the kHz-range electroneurogram (ENG). Existing integrated wearable solutions for minimally invasive biopotential recordings are limited in detection range and accuracy due to trade-offs in bandwidth, noise, input impedance, and power consumption. This article presents a 16-channel wide-band ultra-low-noise neural recording system-on-chip (SoC) fabricated in 65nm CMOS for chronic use in mobile healthcare settings that spans a bandwidth of 0.001 Hz to 1 kHz through a featured sample-level duty-cycling (SLDC) mode. Each recording channel is implemented by a delta-sigma analog-to-digital converter (ADC) achieving 1.0 μ V rms input-referred noise over 1Hz-1kHz bandwidth with a Noise Efficiency Factor (NEF) of 2.93 in continuous operation mode. In SLDC mode, the power supply is duty-cycled while maintaining consistently low input-referred noise levels at ultra-low frequencies (1.1 μV rms over 0.001Hz-1Hz) and 435 M Ω input impedance. The functionalities of the proposed SoC are validated with two human electrophysiology applications: recording low-amplitude electroencephalogram (EEG) through electrodes fixated on the forehead to monitor brain waves, and ultra-slow-wave electrogastrogram (EGG) through electrodes fixated on the abdomen to monitor digestion.

Low Power Design of Efficient Wireless Sensor Node

Abstract: The escalating demand for rapid, efficient System on Chip (SoC) designs has intensified the need for low-power solutions, particularly in Wireless Sensor Nodes reliant on battery power. This research centers on leveraging clock gating to curtail dynamic power usage in an 8-bit Arithmetic and Logic Unit (ALU). Employing the Hans-Carlson Adder for addition and a 4x4 approximation multiplier, the ALU processes data from a humidity sensor module. Simulations using Xilinx Vivado reveal a substantial 65–73% reduction in power consumption at higher frequencies. This ALU, adept at minimizing power, emerges as a viable processing element for energy-sensitive sensor node applications, ensuring prolonged operational longevity.

Hardware Sequence Combinators

Recent advances in formal methods for constructing parsers have employed the notion of combinators: primitive elemental parsers with well-defined methods for combining them in sequences or through choice. This paper explores the subtleties associated with leveraging sequence combinators to produce compact, custom hardware traffic validators. This involves a fully automated process that takes as input a formal grammar specifying message formats and produces a parsing circuit capable of validating traffic headers and payload content. The resulting circuit is deployed through network guard appliances that employ Field Programmable Gate Array (FPGA) devices, or alternatively, within the on-chip FPGA associated with System-on-Chip (SoC) devices, such as the Xilinx UltraScale MPSoC. Each guard appliance acts as a hidden “bump-in-the-wire” that either forwards or drops individual packets based on the message parsing outcome, thereby hardening network segments against zero-day attacks and persistent implants. Guards may operate on a wide variety traffic protocols and formats including TCP/IP, CAN/J1939, or MIL-STD-1553. The central step in parser construction is to build a collection of standard shift/reduce parsing tables that can be employed by a push-down automata to check each byte in a message. Typically, these tables are sparse, resulting in excessive use of FPGA circuit resources to represent them. By leveraging sequence combinators, along with other optimizations, we have been able to produce highly compact representations that can reduce table size by up to 95% for non-trivial grammars. Depending on the grammar, this translates directly into FPGA resource reductions. The reductions now make it viable to implement complex parsers on small, inexpensive FPGA’s, or alternatively combine parsers with encryption and encapsulation to enhance guard capabilities.