System-level Electrostatic Discharge Research Articles

Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit

Electrostatic discharge (ESD) and electromigration are critical issues that significantly impact the reliability of ICs. While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention, potentially compromising IC reliability. This work analyzes various types of metal with different lengths, widths, and angles commonly used in ESD protection circuits in the CMOS process. The objective is to observe their behavior under continuous ESD zapping. The ESD-induced electromigration of metallization in the CMOS process has been analyzed, and metal sensitivity to system-level ESD events has also been identified. It is also analyzed from the perspective of energy that the ESD energy that metal can withstand will decrease as the ESD voltage increases, which will be even more detrimental to the ESD reliability of ICs. The findings from this study aim to provide valuable insights for designing metal lines in ICs to enhance ESD protection.

ESD Research of SCR Devices under Harsh Environments.

In prior technology, system-level electrostatic discharge (ESD) tests under environment change conditions mainly focused on testing the effect of a high-temperature environment. i.e., the effect on internal circuits of heat generated outside. However, few studies have explored the effect of ambient relative humidity changes on integrated circuits (ICs). Therefore, this study will analyze the performance of various ESD protection components under high ambient temperature and high ambient relative humidity. The ESD protection devices are tested for the ESD robustness of the silicon-controlled rectifiers (SCR) under a harsh environment and the measurement results are discussed and verified in the CMOS process.

π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology

CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications.

System-Level ESD-Induced Voltage Fluctuation to the Power of Integrated Circuits on System Board

Based on the voltage and current waveforms, the mechanism of the system-level electrostatic-discharge (ESD) induced the voltage fluctuation to the power of integrated circuits (ICs) on system board is studied. When a contact discharge ESD test is performed at a connector pin, which is terminated with an I/O pin of an IC, not all the current from the system-level ESD may flow through the IC to the ground of the system board. So, the remaining currents can only flow through the power line of the ICs and the connection wire into the power supply to the ground. The power supply has the feedback and pulsewidth modulation circuits to regulate its output voltage. Therefore, the output current of the power supply will interact with the remnant current from the ICs on system board, resulting in the current flowing through the connection wire in the microelectronics system back and forth. Hence, the power of system board will be pulled up and down by the connection wire based on L·(dI/dt), since it acts as an inductor during the alternating current. With the voltage swinging up and down, the p-n junctions in the power domain seems to be driven into the avalanche breakdown or forwarded to generate a lot of electrons and holes inside the ICs, leading to the latch-up event at the low latch-up immunity region.

Editorial Introduction to the Special Issue on Electrostatic Discharge and Immunity—From IC to System

The papers in this special issue focus on scientific contributions in the field of electrostatic discharge (ESD) and immunity—from integrated circuits (ICs) to system. ESD can damage or disrupt electronic systems. With continued scaling of ICs, a combined approach of IC and system forms the best path for understanding and ensuring robustness. This relates to the IC itself: input/output (I/O) structures, power distribution network (PDN), interfaces between IP blocks, as well as the interaction of external protection devices with internal ESD protection structures during system level stress. To effectively protect the ICs fabricated in the advanced nanoscale CMOS processes, the turn-on speed of ESD protection devices must be enhanced to quickly discharge ESD current before the internal circuits are damaged by ESD stresses. Not only component level ESD events, the system level ESD test specified in the IEC 61000-4-2 standard has been used to verify ESD immunity of the microelectronics products. During system level ESD testing, the ESD problems relates to soft failures. So far, only few models for soft failures have been reported. It becomes visible that well designed hard failure protection can also reduce the likelihood of soft failures as most of the current is diverted from the IC and will not disturb the PDN of the IC. ESD robustness in the system level and component level are both important to meet the electromagnetic compatibility (EMC) regulations and/or standards in the industry.

Accurate and Efficient Computation of System-Level ESD Noise Waveforms in ISO 10605 Standard Using Decomposition Method and Split-Domain Approach

In this article, an accurate and efficient computational method of system-level electrostatic discharge (ESD) noise waveforms in a field-coupled ESD test of the ISO 10605 standard using a 3-D full-wave solver is proposed. To apply efficient computational methods to the ESD test simulation, the split-domain approach and decomposition method are first individually validated with a simple structure. Next, a method simultaneously using the decomposition method and split-domain approach is proposed and validated with the separately given field source data. Using the proposed method with the measured electromagnetic fields radiated from an ESD generator, the ESD noise waveforms in the ISO 10605 field-coupled ESD test are accurately and efficiently computed by considering not only the ESD current coupling but also the radiated coupling from the ESD generator.

Statistical Learning of IC Models for System-Level ESD Simulation

To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I–V</i> model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators.

3-D TCAD Methodology for Simulating Double-Hysteresis Filamentary I–V Behavior and Holding Current in ESD Protection SCRs

Current filament (CF)-related double-hysteresis I-V behavior and holding current, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD</sub> ,are analyzed using experiments and 3-D technology computer-aided design (TCAD) simulation in silicon-controlled rectifiers (SCR) for system-level electrostatic discharge (ESD) protection. Our 3-D TCAD methodology uses up and down quasi-dc current sweeps to reveal a memory effect in the current density distribution along the device width. I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> is related to the smallest possible CF where the self-sustaining SCR action takes place during down current sweep. I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD</sub> exhibits a nontrivial dependence on device width, depending on whether a CF is created or not. Analyzing devices of different layouts shows that I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> values determined from experiments and 3-D TCAD are almost layout-independent and substantially lower than those evaluated from 2-D TCAD. I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> calculated by 3-D TCAD in edge-terminated devices is higher than that in 3-D structures obtained from simple width-extended 2-D doping profiles. The use of latter devices, thus, simplifies the 3-D TCAD I- V analysis and provides a safe margin for I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD </sub> prediction. The work is relevant for designing the latch-up immunity of ESD protection devices, and it also shows that conventional 2-D TCAD can provide unwanted overestimation of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HOLD</sub> .

A Physics-based Transient Simulation and Modeling Method for Wide-frequency Electrical Overstress Including ESD

Circuits design that meets various IEC electrical overstress (EOS) standards is still a challenge, for that different kinds of EOS are at different frequency bands. In this paper, a physics-based transient simulation and modeling method is proposed, which can simulate wide-frequency EOS including electrostatic discharge (ESD) and AC characteristics. In this method, the physical model is used to characterize the nonlinear semiconductor devices in the finite-difference time-domain (FDTD)-SPICE co-simulation. Moreover, the modeling and physical parameters extraction method of the ESD protect devices, the transient voltage suppressor diode, is demonstrated. Taking an EOS protection circuit for example, it is modeled and simulated by the proposed method. Moreover, the circuit is also simulated by the widely-used System-Efficient ESD Design (SEED) method, in which the TVS diode is modeled based on 100 ns Transmission Line Pulse (TLP) measurements. The experiments show that both this method and SEED method can characterize the IEC system-level ESD behaviors well. However, the error of the SEED is about 219.2% at 10 MHz AC characteristics, but the maximum error of the proposed method is only 7.8%. Hence, compared with the widely-used SEED method, this method is more accurate when characterizing the EOS event during AC operation and switching.

Transient Analysis of ESD Protection Circuits for High-Speed ICs

Electrostatic discharge (ESD) failures in high-speed integrated circuits (ICs) cause critical reliability problems in electronic devices. Transient voltage suppressor (TVS) diodes are installed on high-speed I/O traces to improve system-level ESD protection. To protect the circuit, the majority of ESD current must flow into the external TVS diode rather than into the IC, but due to turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> behavior, the TVS diode may not snap back when needed and the IC's internal protection may take most of the current. These race conditions between the internal and external ESD protection circuits were investigated for a universal serial bus(USB) interface board. The transient turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> behavior of the on-chip and off-chip protection circuitry was characterized by measurements and by system efficient ESD design (SEED) simulations. The effect of transmission line pulses (TLP pulses) and power supply voltages of different sizes on the response of the protection circuitry were monitored and compared with SEED simulations. SEED models showed good agreement with measurements and were used to study the impact of passive components added to a high-speed trace or within the IC package on the ESD protection response. Results show the importance of properly accounting for the parasitic resistance and inductance between the on-chip diode and off-chip TVS diode, as well as the length of the transmission line when choosing the external TVS device. Results also show that testing must be performed using mid-level events to account for possible problems due to race conditions.

The Impact of Holding Voltage of Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System With CMOS ICs Under System-Level ESD and EFT/Burst Tests

Transient voltage suppressor (TVS) has been widely used on the printed circuit board (PCB) to protect the microelectronics system against the system-level electrostatic discharge (ESD) and electrical fast transient/burst (EFT/B) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD and EFT/B immunity test, if the TVS were designed with a holding voltage of lower than the operating voltage of the CMOS ICs equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different holding voltages was studied under the system-level ESD and EFT/B immunity test. By monitoring the transient voltage waveforms in the time domain during system-level ESD and EFT/B immunity test, the system malfunction has been found when the TVS is with a lower holding voltage. Therefore, the holding voltage of the TVS must be greater than the system operating voltage to maintain the signal integrity in the field applications.

Analysis of the ESD Reconstruction Methodology Based on Current Probe Measurements and Frequency Response Compensation for Different ESD Generators and Severity Test Levels

System-level electrostatic discharge testing according to IEC 61000-4-2 has been the main standardized electrostatic discharge immunity testing procedure for the last few decades. The correlation between a failed test result and the injected electrostatic discharge current waveform characteristics, as well as the reduced reproducibility of the standard methodology, have always concerned product manufacturers and test engineers. In an effort to accurately reconstruct the electrostatic discharge current during immunity testing, researchers are focusing more and more on the usability of current probes in capturing the injected current in “real time”. In this article, the results of a proposed methodology, based on current probe measurements and a frequency response compensation method, published in recent bibliography, for different test levels and electrostatic discharge generators are presented, aiming to highlight the advantages and disadvantages of the method, investigate its universal applicability, and introduce points of future work toward the current reconstruction during system-level electrostatic discharge testing effort.

Field source extraction of an ESD generator and its application to system-level ESD analysis in a solid-state storage system

System-level electrostatic discharge (ESD) noise due to electromagnetic fields radiating from an ESD generator were measured and analyzed in a solid-state drive (SSD) storage system. The field sources of an ESD generator were efficiently modeled from the measured tangential magnetic fields in front of a ESD generator. The extracted field sources were incorporated into a full-wave solver, and the fields inside the disk-array enclosure (DAE) were simulated and validated by comparing to measured fields. The field source models of the ESD generator were then also utilized to predict transient ESD-induced noise voltages in a simplified SSD. Finally, the coupling mechanism and the effects of the DAE geometry were investigated.

Rapid characterization of efficient system level ESD protection strategy using coupling transfer function

This study details a new technique for the fast and efficient design and analysis of system level electrostatic discharge (ESD) protection strategy using developed coupling transfer impedance function. The transfer coupling characteristics from the zapping point to the victim location on a DUT can be computed using coupling transfer gain function. Subsequently, it is integrated with an ESD current source in a SPICE type circuit simulator for the fast and efficient analysis of induced ESD coupling noise and the design of the appropriate ESD protection scheme with the suitable choice of ESD protection device (diodes, SCR, GGNMOS, GCNMOS etc.). The study discusses the different protection schemes i.e. primary, secondary and double ESD protections, and the effect of the selected diode types and ESD stressing levels on the employed protection strategy. The proof-of-concept is validated through the rapid design of suitable system level ESD protection strategy for a microstrip-line PCB, high-speed mobile device memory module, and a portable notebook motherboard.

A Cost-Effective Structure for Secondary Discharge Control to Improve System-Level ESD Immunity of a Mobile Product

A structure embedded in a printed circuit board is proposed to control secondary discharge currents and improve the system-level electrostatic discharge (ESD) immunity for a mobile product with a metal frame. Noise voltages and discharge currents were measured and analyzed according to several secondary discharge paths, such as an air arc, a voltage suppressor device, and with the interlaced suppression device. ESD events that caused soft failures of a real commercial mobile product were tested while a high-definition video was playing. System-level ESD-induced noise and soft failures were cost effectively reduced by the interlaced suppression device.

Area-Efficient On-Chip Transient Detection Circuit for System-Level ESD Protection Against Transient-Induced Malfunction

A new on-chip transient detection circuit with superior area efficiency is proposed against the system malfunction resulting from system-level electrostatic discharge (ESD) events. With dual-latched structure, a better area efficiency can be achieved by the reduced time constant inquiry. The proposed transient detection circuit with a silicon area of 40 ${\mu }\text{m}\,\,{\times }\,\,60\,\,{\mu }\text{m}$ has been fabricated in a 0.18- ${\mu }\text{m}$ CMOS process with 1.8-V devices. The detection sensitivity has been successfully verified under ±200 V system-level ESD tests. To achieve the “Class B” specification of IEC 61000-4-2 standard, the proposed transient detection circuit serves as a safety guard for the system. Through the hardware/firmware co-design, the auto-recovery procedure can be activated by the proposed transient detection circuit sending out a warning signal. With the proposed transient detection circuit co-works with the system program, the immunity level of microelectronic products against the electromagnetic compatibility (EMC) of ESD events can be effectively improved.

Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes on the high-speed DRAM modules (DDR3 and DDR4) against injected ESD noise are determined through full-wave numerical simulations of the memory modules using the developed 3D model of the ESD gun. The validity of the full-wave numerical setup is confirmed through measurements, prior to the DOE analysis. Besides, current distribution analysis of DRAMs, seven different DOE configurations based on the number of installed decoupling capacitors (decaps) and their values on memory modules, are analyzed. The findings of DOE analysis suggests that DDR4 is less susceptible (70–80 % less) to the coupled ESD noise compared to DDR3. In addition, the command address (CA) nets are most sensitive in both memory modules. The utilization of the maximum possible number of decaps covering low, medium and high frequency ranges, as well as separate power and ground layers in memory stack-up design, increase the robustness and immunity of memory modules for the transient ESD event. The suggested approach offers time-saving and financial advantages to high-speed memory community, with the robust design of the memory products at the design stage before the start of the production phase.

Bringing the SEED Approach to the Next Level: Generating IC Models for System ESD and Electrical Stress Simulation out of Design Data

System-level electrostatic discharge (ESD) robustness design according to ISO10605 or IEC 61000-4-2 on printed circuit board (PCB) level is still a challenge). The blocking point is often the lack of accurate models of complete integrated circuits (ICs). Previously published methodologies to generate ESD models for ICs are all based on measurements of the complete IC, showing the drawback of complex, difficult and time-consuming measurements. This paper proposes a novel methodology to generate ESD models for complete ICs out of their design data. The proposed approach requires no measurements with the complete IC and hence can reduce the effort significantly. Furthermore, the methodology offers the possibility for automation, which further reduces the number of needed resources. It is based on the approach of black box modeling. This means simplified behavioral models are used, which contain solely the characteristic behavior in case of disturbance pulses. The methodology focuses on the transient behavior as well as the physical destruction limits of smart power products. Behavioral model in this context means the transient response due to disturbance pulse in terms of voltage drops and current drain. The procedure is explained and verified step by step on an exemplary product. It can be easily transferred to other products. System designers receive a powerful model for targeting certain robustness of their system against transient disturbances. Further enhancements of the methodology can enable also the soft failure assessment by simulation.

Codesign of Electrostatic Discharge Protection Device and Common Mode Suppression Circuit on Printed Circuit Board

A codesign of an electrostatic discharge (ESD) protection device and a common-mode suppression circuit on printed circuit board (PCB) for high-speed input/output interfaces is introduced in this paper. The characteristic and the circuit model of the ESD protection device are investigated and applied into the design of the common-mode suppression circuit. The proposed one-stage design of two-layered PCB structure performs –10-dB common-mode noise suppression from 2.22 to 2.76 GHz; the proposed two-stage design with additional common-mode suppression unit performs wideband suppression from 2.25 GHz to over 8 GHz, covering IEEE 802.11ac WiFi band with –20-dB suppression level. The mode conversion for both designs is lower than –30 dB. The signal integrity and the ESD protection function of proposed design are investigated by eye diagram measurement and system-level ESD simulation. The proposed PCB design provides a low-cost solution for the integration on the high-speed input/output interface of next generation.

System Level ESD Coupling Analysis Using Coupling Transfer Impedance Function

This paper proposes a novel way for the estimation of the system level electrostatic discharge (ESD) coupling using the frequency-domain measurements. ABCD parameters are calculated from the measured (simulated) S-parameters of the equipment under test (EUT). The transfer function of the system level ESD coupling is derived from the ABCD-parameters. The derived transfer function estimates the induced coupling to the EUT quite well for the input ESD stressing. For the ESD source modeling, a novel simple and efficient circuit model of ESD generator is also presented. A good agreement is obtained between the measured and simulated results based on derived coupling transfer impedance function. The proposed method permits the efficient ESD coupling analysis without the need of additional electromagnetic modeling of EUT and ESD generator for various ESD input voltage levels.