The Impact of Holding Voltage of Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System With CMOS ICs Under System-Level ESD and EFT/Burst Tests

Yu-Shu Shen,Ming-Dou Ker

doi:10.1109/ted.2021.3063208

Abstract

Transient voltage suppressor (TVS) has been widely used on the printed circuit board (PCB) to protect the microelectronics system against the system-level electrostatic discharge (ESD) and electrical fast transient/burst (EFT/B) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD and EFT/B immunity test, if the TVS were designed with a holding voltage of lower than the operating voltage of the CMOS ICs equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different holding voltages was studied under the system-level ESD and EFT/B immunity test. By monitoring the transient voltage waveforms in the time domain during system-level ESD and EFT/B immunity test, the system malfunction has been found when the TVS is with a lower holding voltage. Therefore, the holding voltage of the TVS must be greater than the system operating voltage to maintain the signal integrity in the field applications.

Highlights

I N ORDER to protect against the damages from electrostatic discharge (ESD), on-chip ESD protection circuits or devices must be integrated into the CMOS ICs to meet the component-level ESD specification [1]
The signal integrity of microelectronics system protected by three commercial Transient voltage suppressor (TVS) with different holding voltages has been investigated in detail under the system-level ESD test and electrical fast transient/burst (EFT/B) test
The failure modes of these failed equipment under test (EUT) do not cause permanent damage on CMOS ICs but the signal-integrity issue is caused by the TVS

Summary

INTRODUCTION

I N ORDER to protect against the damages from electrostatic discharge (ESD), on-chip ESD protection circuits or devices must be integrated into the CMOS ICs to meet the component-level ESD specification [1]. The discrete transient voltage suppressors (TVSs) were added on the printed circuit board (PCB) of the microelectronics system to protect the CMOS ICs against the overstress of the system-level ESD and EFT test. Such TVSs were often placed near to the I/O ports of CMOS ICs and near to the power pins, on the PCB layout. The signal integrity of microelectronics system protected by TVSs with different holding voltages under the system-level ESD test has been investigated [8]. Further study has been investigated in this work, whether the on-board TVS with its holding voltage lower than the system operating voltage did cause any negative impact to the microelectronics system under ESD/EFT test

TVS CHARACTERISTICS

DC I–V Characteristics of TVS

Test Setup for System-Level ESD Immunity Test

Transient Response Under System-Level ESD Test

Additional Verification on Transient Response

CONCLUSION