Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

Jawad Yousaf,Wansoo Nah,Jinsung Youn,Muhammad Faisal

doi:10.3390/electronics8020210

Abstract

This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes on the high-speed DRAM modules (DDR3 and DDR4) against injected ESD noise are determined through full-wave numerical simulations of the memory modules using the developed 3D model of the ESD gun. The validity of the full-wave numerical setup is confirmed through measurements, prior to the DOE analysis. Besides, current distribution analysis of DRAMs, seven different DOE configurations based on the number of installed decoupling capacitors (decaps) and their values on memory modules, are analyzed. The findings of DOE analysis suggests that DDR4 is less susceptible (70–80 % less) to the coupled ESD noise compared to DDR3. In addition, the command address (CA) nets are most sensitive in both memory modules. The utilization of the maximum possible number of decaps covering low, medium and high frequency ranges, as well as separate power and ground layers in memory stack-up design, increase the robustness and immunity of memory modules for the transient ESD event. The suggested approach offers time-saving and financial advantages to high-speed memory community, with the robust design of the memory products at the design stage before the start of the production phase.

Highlights

The occurrence of transient electrostatic discharge (ESD) events results in the malfunctioning of the electronic devices due to the transfer of high amplitude current signals having a short rise time
For the first time, we present a new design of experiment (DOE) based full-wave EM simulation framework for the system level ESD noise coupling analysis of the realistic complete high-speed dynamic random access (DRAM) memory modules
The analysis is conducted for seven different design of experiment (DOE) analysis configurations based on the change in the number of installed decaps and their values for each module

Summary

Introduction

The occurrence of transient electrostatic discharge (ESD) events results in the malfunctioning of the electronic devices due to the transfer of high amplitude current signals having a short rise time. ESD issues are becoming more critical due to the increasing speed of the microelectronic devices (e.g., DRAM memory modules) and stringent quality test passing criterion of the original equipment manufacturer (OEM) [1,2]. The direct or indirect electromagnetic (EM) coupling of the ESD noise to the sensitive module of the device under test (DUT), such as DRAM memory, would change the operational conditions of the complete product (such as a laptop). The soft failure examples include: the incorrect reading or writing of the data to the hard disk (wrong instructions due to command/data bit change); abrupt turn off of the device; and/or the change in the operational condition of the device with a display of wrong output on DUT screen [1,5,6,7,8].

Objectives

Methods

Findings

Conclusion