Bringing the SEED Approach to the Next Level: Generating IC Models for System ESD and Electrical Stress Simulation out of Design Data

Abstract

System-level electrostatic discharge (ESD) robustness design according to ISO10605 or IEC 61000-4-2 on printed circuit board (PCB) level is still a challenge). The blocking point is often the lack of accurate models of complete integrated circuits (ICs). Previously published methodologies to generate ESD models for ICs are all based on measurements of the complete IC, showing the drawback of complex, difficult and time-consuming measurements. This paper proposes a novel methodology to generate ESD models for complete ICs out of their design data. The proposed approach requires no measurements with the complete IC and hence can reduce the effort significantly. Furthermore, the methodology offers the possibility for automation, which further reduces the number of needed resources. It is based on the approach of black box modeling. This means simplified behavioral models are used, which contain solely the characteristic behavior in case of disturbance pulses. The methodology focuses on the transient behavior as well as the physical destruction limits of smart power products. Behavioral model in this context means the transient response due to disturbance pulse in terms of voltage drops and current drain. The procedure is explained and verified step by step on an exemplary product. It can be easily transferred to other products. System designers receive a powerful model for targeting certain robustness of their system against transient disturbances. Further enhancements of the methodology can enable also the soft failure assessment by simulation.