A Physics-based Transient Simulation and Modeling Method for Wide-frequency Electrical Overstress Including ESD

Abstract

Circuits design that meets various IEC electrical overstress (EOS) standards is still a challenge, for that different kinds of EOS are at different frequency bands. In this paper, a physics-based transient simulation and modeling method is proposed, which can simulate wide-frequency EOS including electrostatic discharge (ESD) and AC characteristics. In this method, the physical model is used to characterize the nonlinear semiconductor devices in the finite-difference time-domain (FDTD)-SPICE co-simulation. Moreover, the modeling and physical parameters extraction method of the ESD protect devices, the transient voltage suppressor diode, is demonstrated. Taking an EOS protection circuit for example, it is modeled and simulated by the proposed method. Moreover, the circuit is also simulated by the widely-used System-Efficient ESD Design (SEED) method, in which the TVS diode is modeled based on 100 ns Transmission Line Pulse (TLP) measurements. The experiments show that both this method and SEED method can characterize the IEC system-level ESD behaviors well. However, the error of the SEED is about 219.2% at 10 MHz AC characteristics, but the maximum error of the proposed method is only 7.8%. Hence, compared with the widely-used SEED method, this method is more accurate when characterizing the EOS event during AC operation and switching.