Synchronous Dynamic Random Access Memory Research Articles

A low-cost, 300-MHz, RISC CPU with attached media processor

This paper describes the 300-MHz StrongARM 1500 microprocessor, which is capable of more than two billion 16-b operations per second. Starting with the original StrongARM 110 design, an attached media processor (AMP) has been integrated along with a synchronous DRAM memory controller and separate I/O bus. In addition, several enhancements have been made to the CPU and cache subsystem, and the chip has been shrunk from a 0.35-to a 0.28-/spl mu/m technology. The chip includes 3.3 million transistors and measures 60 mm/sup 2/. It dissipates less than 3 W at 300 MHz at 2.0-V internal, 3.3-V I/O. The chip supports dynamic clock frequency switching for reduced operating power during low performance demands. There are 333 separately conditioned clocks on the chip, For battery-powered applications, V/sub dd/ can be reduced to achieve <0.5 W operation at 150 MHz. The chip is pseudostatic and can support clock stop and quiescent supply current testing. It implements the ARM V4 instruction set [1].

An eight-bit prefetch circuit for high-bandwidth DRAM's

A low-power and area-efficient data path circuit for high-bandwidth DRAMs is described. For fast burst read operations, eight data per data I/O are stored in local latches placed close to sense amplifiers. As implemented in a 16-Mb synchronous DRAM (SDRAM), this 8-b prefetch circuit allows an early precharge command and a fast access time because it provides low-capacitance data lines for segmented bit-line pairs. At a column address strobe (CAS) latency of two and a burst length of four, the SDRAM demonstrates 100-MHz seamless read operations from different row addresses, because the row precharge and read access latencies are hidden during the burst cycles. The layout of the prefetch circuit is not limited by the bit-line pitch, and data path circuits are connected by a second-metal layer over the memory cells. As a result, a small chip size of 99.98 mm/sup 2/ is attained. Low-capacitance data lines and small local latches result in low active power. In a 100-MHz full-page burst mode, the SDRAM with a 1 M/spl times/16-b configuration dissipates 60 mA at 3.6 V.

A 200 MHz register-based wave-pipelined 64 M synchronous DRAM

A new register-based wave-pipelined scheme for synchronous DRAMs (SDRAMs) is proposed. In this scheme, (N-1) registers are located between a read data bus line pair and a data output buffer and (N-1) read data are stored in parallel in these registers, where N denotes the CAS latency. Since the column data path is not divided and the read data is transmitted directly to the registers, the burst read operation can easily be achieved at a higher operation frequency without a large area penalty or degradation of an internal timing margin. Measured results show that the 64 M SDRAM based on the register-based wave-pipelined scheme can operate up to 200 MHz.

High-speed memory architectures for multimedia applications

In order to meet the requirements for multimedia applications, several approaches to DRAM architecture have emerged. Instead of a single, common memory device, several advanced approaches, such as extended data out (EDO) DRAM, and synchronous DRAM (SDRAM) will each play a major role in the future memory market. Furthermore, advanced interface technologies, such as Rambus RAM (RDRAM), RamLink, and SyncLink are very promising for future-generation memory. Also, application-specific memory, such as cache DRAM (CDRAM), enhanced DRAM (EDRAM), and video DRAM (VRAM) offer unique characteristics to improve performance in particular applications. Since it is beneficial to understand which type of high-speed memory can improve the speed performance of a particular system most effectively, this article discusses the fundamental concepts of these recent high-speed performance memory architectures to aid in the selection of memories for multimedia applications.

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking

A 1.5-W single-chip MPEG-2 MP@ML real-time video encoder large scale integrated circuit (LSI) has been developed. To form an MPEG-2 encoder system, we employ two 16-Mb synchronous DRAM's, a microprocessor unit (MPU), and an audio encoder LSI. Owing to a two-step hierarchical search scheme and a novel adaptive search window scheme, the search range of motion estimation is -48/+47 horizontal and -96/+15.5 vertical, and the pseudo search range, which is the size when the location of the search window is adaptively shifted, is -96/+95 horizontal and -32/+31.5 vertical. We have also developed low-power clocking techniques, i.e., demand-clock controller, local-clock controller, and low-power flip-flops, which can eliminate waste of power in clocking. We have successfully fabricated these new designs as a low-power single-chip MPEG-2 encoder LSI. The operating frequency except for a synchronous DRAM interface unit and a video in/out unit is 54 MHz. The supply voltage to the first and second search engines in a motion estimation unit can be successfully lowered to 2.5 V and the others are 3.3 V. Into a 12.45/spl times/12.45 mm/sup 2/ chip with 0.35-/spl mu/m CMOS and triple-metal layer technology are integrated 3.1 M transistors.

A study of pipeline architectures for high-speed synchronous DRAMs

The performances of SDRAMs with different pipeline architectures are examined analytically on the basis of the time required to refill the on-chip cache of a Pentium CPU. The analysis shows that the cycle time of the conventional pipeline structures cannot be reduced because of its difficulty in distributing the access time evenly to each pipeline stage of the column address access path. On the contrary, the wave pipeline architecture can make the access path evenly divided and can increase the number of pipeline stages to achieve the shortest cache refill time. But the wave congestion at the output terminal of the wave pipeline path caused by access time fluctuation narrows the valid time window. The parallel registered wave pipeline architecture can remove the effect of access time fluctuation so that the cycle time is defined only by the data pulse width. If the data pulse width t/sub w/<2 ns, even 500-MHz clock frequency can be obtained.

A 256-Mb SDRAM using a register-controlled digital DLL

This paper describes the key technologies used in a 256-Mb synchronous DRAM with a clock access time of 1 ns. This DRAM is stable against temperature, voltage, and process variation through the use of a register-controlled digital delay-locked loop (RDLL). The total timing error of the RDLL is about 0.4 ns, sufficient for high frequency operation at 150 to 200 MHz. Unlike most conventional high-density DRAMs, the bit lines are placed above the storage capacitors in this DRAM to relax the design rules of the core area. The noise issues were analyzed and resolved to help implement the technology for mass production of 0.28- to 0.24-/spl mu/m 200-MHz DRAMs.

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 /spl mu/m/sup 2/ cell and 581.8 mm/sup 2/ small die area are achieved using 0.15-/spl mu/m CMOS technology. The /spl times/61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described.

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm/sup 2/ has been fabricated using 0.16 /spl mu/m four-poly, four-metal CMOS process technology.

A full bit prefetch DRAM sensing circuit

A DRAM sensing circuit that achieves both a fast RAS access time and a high-bandwidth burst operation is proposed. For the data burst capability of synchronous DRAM's, 256-bit-long data I/O lines are divided into eight segments. A small local latch is provided for each segment of 32 bit-line pairs to prefetch eight data out of the 256 sense amplifiers. A local buffer is connected to eight local latches through selection switches. Burst read operations, up to eight bits, are done by activating selection switches and the local buffer serially. Besides this prefetch capability, the segmented data I/O line results in very small capacitance, only 0.09 pF. The sensing scheme uses nMOS bit switches and a full Vdd precharge voltage for bit and segmented data I/O lines. Then, after sense amplifiers are turned on, only low-going bit lines are connected to the segmented data I/O lines without any voltage disturbance because of the small capacitance. The proposed circuit, therefore, realizes a high-speed RAS access, which is 16 ns faster than a conventional DRAM. A circuit layout design based on a 0.5-/spl mu/m design rule shows no area impact.

Design and performance evaluation of a pixel cache implemented within application-specific integrated circuits

The application-specific integrated circuit (ASIC) design and the performance of a graphics processor that uses a pipelined-cache with FIFO memory to transfer a 3D pixel array and its z values to the frame buffer in one cycle are described in detail. The functional modules in the graphics processor include: (1) a video refresh converter, (2) a module that combines texture-mapped patterns onto Phong-shaded surfaces, and (3) a bidircctional parallel link between external devices and the frame-buffer modules. Digital differential analyzer (DDA) algorithms and the size of the pixel cache relative to the frame-buffer bandwidth, have been selected for good overall performance. A drawing speed of 8 ns/pixel (32 bits/pixel) or 1.2 million Phong-shaded polygons/s (100-pixel polygons, texture mapped with hidden surface removal) was achieved when 60-ns accesstime single port DRAMs and synchronous DRAMs were used.

Two-chip MPEG-2 video encoder

Our two-chip, real time, MPEG-2, simple-profile-at-main-level encoder supports NTSC 4:2:0 video signals with only three external memories. We have developed a compact encoder chip set. The key features of this chip set are a low encoding delay based on a simple profile at main level; wide-range motion estimation, which it performs using a hierarchical search; a flexible, macroblock level pipeline architecture based on RISC CPUs; and three small peripherals with no glue logic: a VRAM, synchronous DRAM, and FIFO DRAM.

SyncLink: high-speed DRAM for the future

In 1987 it was becoming apparent that computer systems would need to communicate at data rates beyond the capabilities of then current approaches. To take on this challenge, the IEEE Futurebus group formed a new group dedicated to building a fast, coherent interface, scalable from the smallest computer to the largest mainframe. The IEEE officially established the SCI (Scalable Coherent Interface) working group, referenced as IEEE P1596, in 1988. Today the SCI is IEEE Std 1596. It has several derivatives that enhance its operation and meet additional needs such as real-time operations: a differential voltage specification (IEEE 1536.3), a point-to-point memory interface (IEEE 1596.4), and SyncLink (IEEE P1596.7). SyncLink is a new, high-speed memory interface that combines synchronous dynamic RAM (SDRAM), developed in the late 1980s, and the IEEE's RamLink interface, developed in 1990. SyncLink uses the earlier interface's packet protocol as a base but eliminates its point-to-point link to reduce latency. The new interface uses SDRAM's internal pipelining and control for efficient bus utilization. It allows access in the lowest latency possible for a very high bandwidth DRAM. Future plans include data rates of 800 Mbits per pin per second in 1998, to double in the early 2000s. This rate will allow systems to operate at full capability, even when running 3D graphics.

Designing the MPC105 PCI bridge/memory controller

The MPC105 peripheral component interconnection bridge/memory controller provides a platform-specification-compliant bridge between Power PC microprocessors and the PCI bus. With it, designers can create systems using peripherals already designed for a variety of standard PC interfaces. This bridge chip also integrates a secondary cache controller and high-performance memory controller that supports DRAM or synchronous DRAM and ROM or flash ROM.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Considerations for system development of one-chip video MUSE (HDTV) decoder

This paper describes system considerations in the development of a 3rd generation MUSE, video signal decoder implemented on a single chip. We achieved low cost while improving picture quality through cost effective improvements in the moving picture filter and through development of special interfacing circuitry which made it possible to use low cost general purpose synchronous DRAMs instead of customized FIFO DRAMs. >

A full bit prefetch architecture for synchronous DRAM's

A high performance data path circuit design for Synchronous DRAM's (SDRAM's) is described. Data lines by second-level of metal above memory cells achieve a low power and area efficient full bit prefetch capability. An experimental 3.3-V 16-Mb SDRAM is developed based on this architecture. Since the full burst read data are latched in I/O sense amplifiers by a single CAS access, a precharge operation can start as early as two clocks before the data burst cycles begin. The early precharge function allows next RAS and CAS accesses during burst reads of the previous data. With a burst length of eight, a seamless read operation is possible for any row addresses even within the same bank. The full bit prefetch architecture enables low active power data burst operations because high frequency clock driven circuits are limited to the data path only. The SDRAM with a 1M/spl times/16-b configuration dissipates a 65-mA active current at a 100-MHz full page mode operation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture

A 3.3-V 512-k/spl times/18-b/spl times/2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm/sup 2/, which is the same die size as the conventional DRAM, has been achieved with 0.50-/spl mu/m CMOS process technology. >

16-Mb synchronous DRAM with 125-Mbyte/s data rate

In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M/spl times/8) achieves a 125-Mbyte/s data rate using 0.5-/spl mu/m twin well CMOS technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 32-bank 256-Mb DRAM with cache and TAG

A 125 megabyte/s synchronous 32-bank 256-Mb DRAM has been developed by a bank-interleaving oriented multibank architecture including a shared-sense amplifier cache with an overlapped bank control for hidden precharge, phase-aligned timing pulse transmission, and voltage controlled negative conductance (VCNC) data-bus current sense amplifier.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

QCD teraflops computer

Architectural enhancements are described to increase the performance of the arithmetic accelerator and memory of the nodes in the CM-5 for QCD and a broad range of general problems while maintaining compatibility with existing software, compilers, communications network and I/O subsystems. A factor of 10 increase in performance is obtained by increasing the number of floating point processors by a factor of 4, extending the vector instruction set for dual execution of single-precision arithmetic, and increasing the block rate from 32 to 40 MHz. The required memory bandwidth is obtained by using synchronous DRAMs and 4 floating point processors are packaged into a multichip module which occupies the same area as a present processor package. The proposed 2048 node machine will provide 2.6 Teraflops peak, 0.5 – 1.5 Teraflops sustained on lattices of 32 2 × 64 − 128 3 × 256, will have 256 Gigabytes of memory, 1 Terabyte of disk, an estimated cost of approximately $40 million, and can be built in 2.5 years.