Abstract
Architectural enhancements are described to increase the performance of the arithmetic accelerator and memory of the nodes in the CM-5 for QCD and a broad range of general problems while maintaining compatibility with existing software, compilers, communications network and I/O subsystems. A factor of 10 increase in performance is obtained by increasing the number of floating point processors by a factor of 4, extending the vector instruction set for dual execution of single-precision arithmetic, and increasing the block rate from 32 to 40 MHz. The required memory bandwidth is obtained by using synchronous DRAMs and 4 floating point processors are packaged into a multichip module which occupies the same area as a present processor package. The proposed 2048 node machine will provide 2.6 Teraflops peak, 0.5 – 1.5 Teraflops sustained on lattices of 32 2 × 64 − 128 3 × 256, will have 256 Gigabytes of memory, 1 Terabyte of disk, an estimated cost of approximately $40 million, and can be built in 2.5 years.
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