Implementation and Optimization of Throughput in High Speed Memory Interface Using AXI Protocol

Abstract

The current challenge is to meet out the compatibility of data rates between the data processing systems and the memory bandwidth requirements. For a stream oriented data, Double Data Rate Type three (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) memory interface boosts the buffering capability for processing applications. In this paper, We mainly focus on optimizing the throughput of a high speed DDR3 memory interface using the Advanced eXtensible Interface (AXI) protocol containing independent read/write channels. We have designed the user defined logic in the AXI master to command the AXI slave viz., DDR3 memory. The final design is implemented in the Microsemi RTG4 series FPGA and operated at the frequency of 320 MHz. The design is articulated to achieve maximum throughput by designing AXI master without write response states.