A Novel Design of High-speed Multi-port Memory Interface for Digital Signal Processor

Abstract

With the improvement of Digital Signal Processor (DSP)’s ability to process data, the requirement for memory access is higher and higher. In order to ensure the real-time performance of data processing, multiple processing stages including scalar execution level, access memory level in DSP core and peripherals like debug, the Host Port Interface (HPI) in DSP system needs to fetch or store data from memory more quickly. To solve this practical problem, this paper introduces a multi-port memory interface (MPMI) based on Advanced eXtensible Interface 4 (AXI4) bus protocol, which can connect multiple access ports in DSP system with Double Data Rate 4 (DDR4) Synchronous Dynamic Random Access Memory (SDRAM). The design has successfully passed the verification of various reading and writing scenarios, and the novel combination of fixed and polling priority makes the interface’s access efficiency increase by 32% compared with the one using a normal polling priority.