Memory subsystem technology and design for the z990 eServer

Abstract

This paper discusses the technology and design of the first double data rate (DDR) memory subsystem for the IBM zSeries® eServer™. The main storage subsystem accommodates the frequency mismatch between the memory controller and industry-standard synchronous dynamic random-access memory (SDRAM), protects data through error-correction code and SDRAM sparing, and increases overall memory subsystem bandwidth. Each memory card consists of the first synchronous memory interface (SMI) application-specific integrated circuit (ASIC) that is optimized specifically for DDR applications, the SMI-enhanced (SMI-E). The SMI-E controller data interface communicates with the high-speed memory controller on the multichip module through special phase alignment and elastic buffering circuitry that determines the optimal sampling point to reliably receive data from the controller. The SMI-E memory data interface is connected to registered DDR dual inline memory modules running up to 250 Mb/s using 256-Mb and 512-Mb SDRAM technology, thereby allowing memory card densities between 4 GB and 32 GB per card. Because of the increased DDR memory interface bit rates, special attention was paid to the design of the SMI-E substrate and base card to minimize noise. The memory, when used in a fully populated system, has four times more storage capacity than the previous z900 generation.