Unaligned Burst-Aware Memory Subsystem

Abstract

In this paper, we present a memory subsystem for a burst that is unaligned to a block of synchronous dynamic random access memory (SDRAM) columns. In the case that a processor demands such an unaligned burst, a memory subsystem is required to rearrange SDRAM transfers in the order demanded by the processor. Our memory subsystem modifies a memory address given by a processor, then accesses SDRAMs with the modified memory address, and thus makes SDRAMs output transfers in an intermediate order. The transfers can be rearranged in the order demanded by the processor with the minimal performance degradation. Next, urgent transfers within the burst are delivered via priority service, and nonurgent transfers within the burst can be independently delivered via best-effort service. Experimental results show that the proposed memory subsystem achieves, on average, 16.6% shorter program execution time and 13.5% shorter memory latency than a conventional memory subsystem for wrapping bursts in the case that a quadcore processor concurrently executes four benchmarks. In addition, the proposed memory subsystem achieves, on average, 5.4% shorter application execution time and 3.4% shorter memory latency than a conventional memory subsystem for incrementing bursts in case of double data rate (DDR) 3 SDRAMs.