A full bit prefetch architecture for synchronous DRAM's

Abstract

A high performance data path circuit design for Synchronous DRAM's (SDRAM's) is described. Data lines by second-level of metal above memory cells achieve a low power and area efficient full bit prefetch capability. An experimental 3.3-V 16-Mb SDRAM is developed based on this architecture. Since the full burst read data are latched in I/O sense amplifiers by a single CAS access, a precharge operation can start as early as two clocks before the data burst cycles begin. The early precharge function allows next RAS and CAS accesses during burst reads of the previous data. With a burst length of eight, a seamless read operation is possible for any row addresses even within the same bank. The full bit prefetch architecture enables low active power data burst operations because high frequency clock driven circuits are limited to the data path only. The SDRAM with a 1M/spl times/16-b configuration dissipates a 65-mA active current at a 100-MHz full page mode operation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>