Synchronous Dynamic Random Access Memory Research Articles

第二代雙倍資料率記憶體(DDR2 SDRAM)電路佈線性能穩定度之研究

With the increase of CPU operating frequency, the data that the computer deals with will increase relatively. We need faster memory to deal with the data transmitted when designing product. Original memory is only access data in the rising time, changed into assess data in rising time and falling time; this is DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). When the speed of access data still can't keep up with the speed of CPU, we improve DDR SDRAM. Upgrade 2 bits Pre-fetch of DDR DRAM to 4 bits Pre-fetch, this is DDR2 SDRAM. In this paper, we propose the method and standard of PCB layout of DDR2 SDRAM. In the mean time, we take demand for Timing standard of a DDR2 SDRAM as an example, to design PCB layout of DDR2 SDRAM module. And measure its address signals, data signals and control signals with oscilloscope, according to the time sequence of pulse movements of synchronous. In DDR2 SDRAM module that pulse movements of synchronous controls, when the pulse was transferred to the status, Set-up Time and Hold Time of address signals, data signals and control signals should all keep its standard. In this article gives an example the PCB wiring, its presents Set-up Time and Hold Time all conform to the standard. Sufficiently proof the PCB wiring method and the criterion of DDR2 SDRAM module may do for the industrial related design reference.

Real-time video stabilisation

This paper deals with image stabilisation for video-based tracking systems. An introduction to image stabilisation is stated. A short description of known algorithms for image stabilisation follows, including our solution based on these methods with some optimisations. At the end, we represent a suitable hardware platform, which we developed and constructed and uses Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA) and Synchronous Dynamic Random Access Memory (SDRAM). This device is under testing now.

Radiation Test Challenges for Scaled Commercial Memories

As sub-100 nm CMOS technologies gather interest, the radiation effects performance of these technologies provide a significant challenge. In this paper, we shall discuss the radiation testing challenges as related to commercial memory devices. The focus will be on complex test and failure modes emerging in state-of-the-art flash non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs), which are volatile. Due to their very high bit density, these device types are highly desirable for use in the natural space environment. In this paper, we shall discuss these devices with emphasis on considerations for test and qualification methods required.

Improving SDRAM access energy efficiency for low-power embedded systems

DRAM (dynamic random-access memory) energy consumption in low-power embedded systems can be very high, exceeding that of the data cache or even that of the processor. This paper presents and evaluates a scheme for reducing the energy consumption of SDRAM (synchronous DRAM) memory access by a combination of techniques that take advantage of SDRAM energy efficiencies in bank and row access. This is achieved by using small, cachelike structures in the memory controller to prefetch an additional cache block(s) on SDRAM reads and to combine block writes to the same SDRAM row. The results quantify the SDRAM energy consumption of MiBench applications and demonstrate significant savings in SDRAM energy consumption, 23%, on average, and reduction in the energy-delay product, 44%, on average. The approach also improves performance: the CPI is reduced by 26%, on average.

적외선검출기 READOUT CONTROLLER 개발

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a <TEX>$512{\times}512$</TEX> InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to <TEX>$5{\mu}m$</TEX>, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).

A 512-Mb DDR3 SDRAM Prototype With&amp;lt;tex&amp;gt;$C_IO$&amp;lt;/tex&amp;gt;Minimization and Self-Calibration Techniques

A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C/sub IO/ minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as temperature read-out from on-chip sensor and per-bank-refresh were also implemented.

The Exit Problem in a Nonlinear System Driven by 1/f Noise: The Delay Locked Loop

The frequency generated by high frequency oscillators contains a small but significant noise component known as phase noise, also known as oscillator noise or phase jitter. The phase noise belongs to the family of stochastic processes with spectra $1/f^\alpha$, which exhibits scaleinvariance (or self-similarity) and a long-term correlation structure that decays polynomially in time. Both the phase and thermal noises cause errors in receivers that contain the oscillators. In particular, they cause losses of lock in phase tracking systems such as the phase locked loop in coherent systems, which include cellular phones, global positioning systems (GPS), and radar (e.g., synthetic aperture radar (SAR)), and in the delay locked loop (DLL), which is an important component of code division multiple access receivers and interface to modern memory modules, such as double data rate synchronous dynamic random access memory. The mean time to lose lock (MTLL) is well known to be an important design objective for various tracking loops. The evaluation of the MTLL is known in the mathematical literature as the exit problem for a dynamical system driven by noise, which is the problem of calculating the mean time for the noisy trajectories to reach the boundary of the domain of attraction of a stable point of the noiseless dynamics. In this paper we develop an analytic approach to the evaluation of the leading order term for MTLL of a second order DLL, due to both the non-Markovian $1/f^\alpha$ noise and to thermal white noise. The method is applicable to more general systems driven by a wide class of phase noises. The keys to the solution of this exit problem are the construction of a series of higher order Markovian processes that converge to the non-Markovian $1/f^\alpha$ noise and the asymptotic solution to a multidimensional elliptic boundary value problem that the mean first passage time (MFPT) satisfies.

과학기술위성 2호 대용량 메모리 유닛 시험모델 설계 및 구현

본 논문에서는 과학기술위성 2호 대용량 메모리 유닛(Mass Memory Unit, MMU)의 시험모델(Engineering Model, EM)을 개발하고 기능 및 성능 시험한 결과를 제시하였다. 성능 구현에 필요한 로직들을 별도의 전용 칩들을 사용하지 않고 하나의 FPGA에 구현함으로써 대용량 메모리 유닛을 소형화, 경량화하고 저전력으로 사용할 수 있도록 하였다. 대용량 메모리는 2Gbits SDRAM 모듈을 사용하였으며 파일 시스템을 운용하여 지상국에서의 데이터 관리가 용이 하도록 하였다. 대용량 메모리에서 발생하는 SEU(Single Event Upset)를 극복하기 위해서 RS(207,187) 코드가 소프트웨어로 구현되어 있어서 187바이트당 10바이트의 에러를 복구할 수 있다. 또한 탑재체 데이터의 수신 성능을 검증하기 위해서 시뮬레이터를 제작 하였다. This paper describes the design and implementation of engineering model(EM) of Mass Memory Unit(MMU) for Science and Technology Satellite 2(STSAT-2) and the results of integration test. The use of Field-Programmable Gate Array(FPGA) instead of using private electric parts makes a miniaturization and lightweight of MMU possible. 2Gbits Synchronous Dynamic Random Access Memory(SDRAM) module for mass memory is used to store payload and satellite status data. Moreover, file system is applied to manage them easily in the ground station. RS(207,187) code improves the tolerance with respect to Single Event Upset(SEU) induced in SDRAM. The simulator is manufactured to verify receiving performance of payload data.

Verification strategy for the Blue Gene/L chip

The Blue Gene®/L compute chip contains two PowerPC® 440 processor cores, private L2 prefetch caches, a shared L3 cache and double-data-rate synchronous dynamic random access memory (DDR SDRAM) memory controller, a collective network interface, a torus network interface, a physical network interface, an interrupt controller, and a bridge interface to slower devices. System-on-a-chip verification problems require a multilevel verification strategy in which the strengths of each layer offset the weaknesses of another layer. The verification strategy we adopted relies on the combined strengths of random simulation, directed simulation, and code-driven simulation at the unit and system levels. The strengths and weaknesses of the various techniques and our reasons for choosing them are discussed. The verification platform is based on event simulation and cycle simulation running on a farm of Intel-processor-based machines, several PowerPC-processor-based machines, and the internally developed hardware accelerator Awan. The cost/performance tradeoffs of the different platforms are analyzed. The success of the first Blue Gene/L nodes, which worked within days of receiving them and had only a small number of undetected bugs (none fatal), reflects both careful design and a comprehensive verification strategy.

Radiation tests of CMS RPC muon trigger electronic components

The results of proton irradiation test of electronic devices, selected for the RPC trigger electronic system of the CMS detector, will be presented. For Xilinx Spartan-IIE FPGA the cross-section for Single Event Upsets (SEUs) in configuration bits was measured. The dynamic SEUs in flip-flops were also investigated, but not observed. For the FLASH memories no single upsets were detected. Only after irradiating with a huge dose permanent damages of devices were observed. For Synchronous Dynamic Random Access Memory (SDRAM), the SEU cross-section was measured.

A temperature-controlled complementary metal oxide semiconductor camera

In recent years, complementary metal oxide semiconductor (CMOS) imaging sensors have been replacing charge-coupled device (CCD) imagers in consumer and industrial markets. Their low cost and high peripheral integration on chip gives new opportunities to those who have not adopted CCD technology due to cost or technical concerns. This paper describes the design of a prototype CMOS camera for use in spectral experiments with noise reduction techniques to improve image quality. We use a Peltier device to cool the sensor, a synchronous dynamic random access memory (SDRAM) frame buffer for storage and a universal serial bus (USB) interface to transfer the data at a high speed.

Memory subsystem technology and design for the z990 eServer

This paper discusses the technology and design of the first double data rate (DDR) memory subsystem for the IBM zSeries® eServer™. The main storage subsystem accommodates the frequency mismatch between the memory controller and industry-standard synchronous dynamic random-access memory (SDRAM), protects data through error-correction code and SDRAM sparing, and increases overall memory subsystem bandwidth. Each memory card consists of the first synchronous memory interface (SMI) application-specific integrated circuit (ASIC) that is optimized specifically for DDR applications, the SMI-enhanced (SMI-E). The SMI-E controller data interface communicates with the high-speed memory controller on the multichip module through special phase alignment and elastic buffering circuitry that determines the optimal sampling point to reliably receive data from the controller. The SMI-E memory data interface is connected to registered DDR dual inline memory modules running up to 250 Mb/s using 256-Mb and 512-Mb SDRAM technology, thereby allowing memory card densities between 4 GB and 32 GB per card. Because of the increased DDR memory interface bit rates, special attention was paid to the design of the SMI-E substrate and base card to minimize noise. The memory, when used in a fully populated system, has four times more storage capacity than the previous z900 generation.

DDR SDRAM을 위한 저전압 1.8V 광대역 50∼500MHz Delay Locked Loop의 설계

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

An open-loop clock deskewing circuit for high-speed synchronous DRAM

An open-loop clock deskewing circuit (CDC) for high-speed synchronous DRAM is described. Unlike the conventional circuits, the CDC does not require an additional measure delay line, thus power consumption is reduced. The delay is measured directly from the main delay line and both the input and output ports of the delay line are movable. The CDC provides a deskewed clock within two clock cycles.

A survey of storage options

Over the past 50 years, technological innovations have continually driven down computer storage costs while dramatically increasing performance and value-and the trend shows no signs of slowing. The article considers various forms of storage including: random access memory; asynchronous and synchronous DRAM; RDRAM; SDRAM; flash memory; tape; RAID storage; hard disk; floppy drives; and CDs and DVDs.

FTC piles onto standardization Rambus' skullduggery

The Rambus standardization skullduggery saga continues. SDRAM technology licensor Rambus sued chipmaker Infineon for patent infringement because Infineon refused to take a license under Rambus' patents. (SDRAMs are synchronous dynamic random-access memory chips. Instead of running asynchronously (like ordinary DRAMs), SDRAMs are refreshed by a synchronous system clock. By 1999, SDRAM had largely replaced asynchronous DRAM.) Infineon then countersued for common-law fraud based on Rambus' alleged abuse of the standard-setting process. After a trial in which the judge assessed $7 million in damages against Rambus, the company appealed to the Federal Circuit appeals court. After its recent hearing of the opposing arguments, the Federal Circuit will probably take at least six months to hand down an opinion. In June 2002, the Federal Trade Commission weighed in by suing Rambus for engaging in unfair competition, in violation of section 5 of the FTC Act.

Logic design and implementation of FPGA for a high frame rate ultrasound imaging system

Recently, a method has been developed for high frame rate medical imaging [Jian-yu Lu, ‘‘2D and 3D high frame rate imaging with limited diffraction beams,’’ IEEE Trans. Ultrason. Ferroelectr. Freq. Control 44(4), 839–856 (1997)]. To realize this method, a complicated system [multiple-channel simultaneous data acquisition, large memory in each channel for storing up to 16 seconds of data at 40 MHz and 12-bit resolution, time-variable-gain (TGC) control, Doppler imaging, harmonic imaging, as well as coded transmissions] is designed. Due to the complexity of the system, field programmable gate array (FPGA) (Xilinx Spartn II) is used. In this presentation, the design and implementation of the FPGA for the system will be reported. This includes the synchronous dynamic random access memory (SDRAM) controller and other system controllers, time sharing for auto-refresh of SDRAMs to reduce peak power, transmission and imaging modality selections, ECG data acquisition and synchronization, 160 MHz delay locked loop (DLL) for accurate timing, and data transfer via either a parallel port or a PCI bus for post image processing. [Work supported in part by Grant 5RO1 HL60301 from NIH.]

High-speed DRAM interface

The data rate of the dynamic random access memory (DRAM) interface has been greatly increased to reduce the performance gap between the DRAM and the central processing unit (CPU). The data rate of double-data rate (DDR) synchronous DRAM (SDRAM) is now exceeding 266 Mb/s/pin while the packet-based RAMBUS DRAM is offering up to 1066 Mb/s/pin data rate. The difference in the data rate is mainly due to their different channel structures. These DRAM interface channels are basically multi-drop bus where a driver should drive multiple loads. The maximum data rate is determined by how the multiple loads are configured. The data rate of the DRAM interface channel has been greatly increased and is expected to exceed 2 Gb/s/pin in the near future. To achieve this goal, the physical interface such as the bus structure should be optimized to minimize the timing uncertainty. The I/O timing circuitry plays an important role in determining the maximum data rate. Thus, the, circuit design should also be focused on minimizing timing uncertainty.

A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique

A quadruple data rate (QDR) synchronous DRAM (SDRAM) interface processing data at 500 Mb/s/pin with a 125-MHz external clock signal is presented. Since the QDR interface has a narrower data timing window, a precise skew control on data signals is required. A salient skew cancellation technique with a shared skew estimator is proposed. The skew cancellation circuit not only reduces the data signal skews on a printed circuit board down to 250 ps, but also aligns the data signals with an external clock signal. The entire interface, fabricated in a 0.35-/spl mu/m CMOS technology, includes a high-speed data pattern generator and consumes 570 mW of power at 3.0-V supply. The active die area of the chip with the on-chip data pattern generator is 2.4 mm/sup 2/.

Another update on standardization skullduggery

This is an update on the May-June and July-August Micro Law columns on recent abuse of the standard-setting process. On 9 August, the trial judge entered about 200 pages of final orders and opinions in the case. The next day, Rambus filed a notice of appeal to the US court of appeals for the Federal Circuit, which will probably take at least a year to dispose of the appeal case. Barring the unexpected, this should be the last you hear about this particular episode of standardization skullduggery for a long time. However, there seems to be no let-up in standardization skullduggery by others. As you may recall, a jury in Richmond, Virginia, found that Rambus, with the aid of a mysterious informant designated Secret Squirrel, defrauded the JEDEC Solid State Technology Association (formerly, the Joint Electronic Devices Engineering Council) and, the dynamic RAM industry. Infineon had alleged that Rambus, manipulated its claims in pending patent applications to cover the evolving JEDEC standards on single-data-rate (SDR) and double-data-rate (DDR) synchronous dynamic RAM (SDRAM) chips. After JEDEC issued the patents and published the standards, Rambus demanded that SDRAM manufacturers take high-priced licenses under the patents. Patent infringement litigation followed when three manufacturers (Infineon, Micron, and Hyundai), refused to take licenses. Infineon's case went to trial first, which led to the fraud verdict. Rambus filed papers with the court explaining why it was not guilty of fraud and asking the court to overturn the verdict and enter in its favor a judgment as a matter of law (JMOL). A JMOL is a judgment that a court enters to overturn a jury verdict because the court believes that no reasonable jury could have reached such a verdict.