Dual-V/sub T/ self-timed CMOS logic for low subthreshold current multigigabit synchronous DRAM

Abstract

A subthreshold current reduction logic, the dual-V/sub T/ self-timed (DVST) logic, is developed for the possible application to multigigabit synchronous DRAM. Minimizing subthreshold current is a critical problem in low-voltage CMOS logic. DVST logic has potential advantages over conventional dual-V/sub T/ logic in terms of circuit delay, subthreshold current, operating voltage, and area consumption. A detailed comparison of the conventional logic and the DVST logic is carried out by SPICE simulation. Methods for the determination of the threshold voltages of low-and high-V/sub T/ MOS transistors, for the optimization of the width of the MOS transistors in the circuit, and for the determination of the delay time of the resetting signal are developed. Examples of basic logic blocks and inverter chains are illustrated with their simulation results. The DVST logic circuit in which the subthreshold leakage current path is blocked by a large high-V/sub T/ MOS transistor can reduce the subthreshold current to the same level of high-V/sub T/ logic. It can operate two times faster than the conventional dual-V/sub T/ logic at 1.0-V supply voltage by removing the limitation in /spl gamma/ of the dual-V/sub T/ logic. In the voltage range of 0.8-1.5 V it operates at even higher speed than the low-V/sub T/ logic and only below 0.7-V supply voltage it is exceeded by the low-V/sub T/ logic. Its application to synchronous DRAM, especially in the wave pipeline architecture of the data path, is described.