Synchronous Counter Research Articles

Vibration Reduction of SRM Through Controlling the Average of Applied Demagnetization Voltage

Although Switched Reluctnace Motors have many advantages, vibration is known as their most severe drawback acting as an impediment limiting their widespread use in industrial and domestic applications. Through electromechanical relationships, it is shown that the first-order time derivative of applied phase voltage and second-order time derivative of radial force directly affect the amplitude of generated vibration, especially at the beginning of demagnetization instance. Therefore, a set of criteria is stated in this paper meeting which ensures having low vibration intensity. In this paper, three types of demagnetization voltages are proposed which comprehensively meet the stated criteria. These voltages share the same characteristics contributing to the vibration reduction in Switched Reluctance Motor. Two vital parameters of Synchronous Counter and Coefficient are included in the proposed demagnetization voltages which must be meticulously chosen in order to be effective. Noticeable contribution of the proposed methods to the vibration alleviation is validated through simulation and experimental tests conducted under different working conditions.

Design of synchronous decimal counter using reversible Toffoli–Fredkin Netlist

Investigations in reversible computation have been one of the notable dimensions among the emerging research domains. Reversible circuits promise near-zero heat dissipation resulting in a considerable amount of literary proposals. This article proposes a reversible synchronous decimal counter using Toffoli and Fredkin gates. Decimal counter forms an important Boolean specification as they are used for clock generators, frequency dividers, clock division, integrated oscillation, etc. Although literature witnesses exhaustive research in reversible mod-2/4/8/16 counters, there is a void in the domain of reversible decimal counters. We propose three designs D1, D2, and D3. Design D1 and D2 are synchronous decimal up and down counters, respectively, using Toffoli Netlist. Design D3 is the integration of designs D1 and D2 using the Fredkin Gate array. The proposed designs have been checked using a state-of-the-art optimization algorithm in literature and the results reflect our design to be best optimized. Peer analysis reflects a summary of existing literary proposals exhibiting the uniqueness of the proposed designs.

A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems

This paper presents the design of a low power, compact multi-channel single-shot time-to-digital converter (TDC) capable of handling multiple hits per channel. The system has 17 hit channels and 1 trigger channel and is designed to meet the requirements of the iron calorimeter detector in the India-based neutrino observatory. The TDC core consists of a delay chain stabilized by a delay-locked loop (DLL) and synchronous counters. The digital backend is programmable to allow for multiple configurations during the operation. The common core to all channels with concurrent accessibility, choice of core clock frequency optimizing the trade-offs between performance, power and area, and optimal backend logic result in a compact and low power design. It achieves a single-shot precision better than 65ps. The 0.13 μm chip occupies an active area of 3.72 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 3.4 mW per channel. This paper also reviews the theory on how timing precision is defined for a single-shot TDC and explains how the test plan can be devised based on the jitter in the system.

An Optimized Counter Design using T Flip-Flop in Quantum-Dot Cellular Automata Technology

Conventional CMOS technology have lot of limitations and serious challenges threat this technology when scaled to a nano-level. Several alternative technologies have been proposed as solutions to overcome limitations and challenges encountered by CMOS. Quantum dot-cellular automata (QCA) is an emerging nanotechnology for the development of logic circuits such as combinational and sequential circuits.QCA seems to be best alternative to the conventional complementary metal-oxide semiconductor (CMOS) technology.QCA is a new computing paradigm in nanotechnology that can implement digital circuits with outstanding features such as ultralow power consumption, faster switching speed and extremely density structure . In this paper , a novel area efficient and optimized QCA layout design of sequential circuit T flip flop is proposed by which the QCA layout area has reduced by 57% , cell count improved by 56% in comparison with the earlier best designs. The use of proposed T flip flop in designing sequential circuits like synchronous 2 bit up counter,3 bit up counter and 4 bit up counter has reduced the QCA layout area by 65%,64% and 68% respectively where as QCA cell count are reduced by 53%, 62% and 59%.. The sequential circuits flip flop and counters are designed using three input XOR gate and are implemented by QCA layout. The paper also present the use of proposed T flip flop designed with 3 input XOR gate in designing not only synchronous binary up counters but also in synchronous binary down counter provides a significant reduction in the hardware and complexity than the existing methods. These circuits are simulated using computer aided design tool QCA Designer 2.0.3, which is a design and simulation tool for quantum dot cellular automata. The aim is to maximize the circuit density and focus on a QCA layout that uses minimal number of cells

A Wide Dynamic Range and Low Bit Error Pixel TDC Suitable for Array Application

This brief presents a cascade pseudo 3-level time-to-digital converter (TDC) based on wideband phase-locked loops (PLLs) for photon time of flight measurement. In each pixel, a 9-bit pseudo random synchronous counter composed of linear feedback shift register is served as a high-level coarse TDC. Its counting clock is directly coming from the synchronous counter served as the middle-level TDC. The low-level fine TDC is based on time-interpolation technology and directly use the low-jitter multi-phase clock signal generated by the PLL to complete the fine quantization of the residue time. In addition, proper timing control and error suppression methods are implemented in the proposed TDC. The circuit is demonstrated in TSMC 0.35- ${\mu }\text{m}$ CMOS process. Under the condition of 10-MHz input reference frequency and 3.3-V supply voltage, the wideband PLL can be locked from 146 to 450 MHz. The resolution of the TDC will change from 856 to 278 ps. At 450 MHz, the measured DNL around $15\boldsymbol {\mu }\text{s}$ is–0.1 to 0.1 LSB and the INL is–0.05 to 0.2 LSB.

Synchronous Counter Design Using Novel Level Sensitive T-FF in QCA Technology

The quantum-dot cellular automata (QCA) nano-technique has attracted computer scientists due to its noticeable features such as low power consumption and small size. Many papers have been published in the literature about the utilization of this technology for de-signing many QCA circuits and for presenting logic gates in an optimal structure. The T flip-flop, which is an essential part of digital designs, can be used to design synchronous and asynchronous counters. This paper presents a novel T flip-flop structure in an optimal form. The presented novel gate was used to design an N-bit binary synchronous counter. The QCADesigner software was used to verify the designed circuits and to present the simulation results, while the QCAPro tool was used for the power analysis. The proposed design required minimal power and showed good improvements over previous designs.

Novel ternary D-Flip-Flap-Flop and counter based on successor and predecessor in nanotechnology

This paper presents a novel design of ternary circuits using carbon nano-tube transistors (CNTFETs). Using multi-valued logic can reduce chip interconnections, which can have a direct effect on chip area and interconnections power consumption. In this paper, at first, a novel design of ternary successor and predecessor is done with one supply voltage and is compared with the previous design based on CNTFETs. It is shown that this new design provides excellent energy efficiency. Furthermore, a novel structure for the D-Flip-Flap-Flop design is proposed by combining the successor and the predecessor; in this D-Flip-Flap-Flop, the second output is the next level of the first output instead of the invert of that, so this D-F.F.F is easily applicable to the counter design. For the first time, two types of ternary synchronous and asynchronous counters are designed based on CNTFETs, which can be extended to the desired bits using the proposed successor and predecessor on the basis of D-Flip-Flap-Flop. Simulation results using HSPICE software and CNT-32 nm model demonstrate that the proposed ternary circuits (successor, predecessor and D-Flip-Flap-Flop) consume significantly lower power, delay and PDP, as compared with the previous works with one supply voltage; Furthermore, the first designs of ternary synchronous and asynchronous counters based on the CNTFETs can function flawlessly with a high performance.

Design of Electronic Virtual Experiment System Based on LabVIEW

For traditional experimental equipment, there are no experimental simulation functions and assistant experimental teaching functions in experimental teaching. A set of virtual experiment system for electronics department was designed by LabVIEW, including the synchronous binary counter virtual experiment and spectrum analyzer virtual instrument. The experimental system possesses distinctive features, such as openness, expansion, interaction, digital, network, module, economy, etc. It is a new experimental teaching method and development direction of experimental teaching innovation, and it will effectively promote teaching concepts and teaching technology. The reform of the model is conducive to improve the teaching conditions and the level of experimental teaching. It is the dominant direction of the reform of hardware experimental teaching based on traditional instruments in colleges and universities.

QDI Constant-Time Counters

Counters are a generally useful circuit that appear in many contexts. Because of this, the design space for clocked counters has been widely explored. However, the same cannot be said for robust clockless counters. To resolve this, we designed an array of constant response time counters using the most robust clockless logic family, quasi-delay-insensitive (QDI) circuits. We compare our designs to their closest QDI counterparts from the literature, showing significant improvements in design quality metrics including transistor count, energy per operation, frequency, and latency in a 28-nm process. We also compare our designs against prototypical synchronous counters generated by commercial logic synthesis tools.

Design Simulations of Synchronous Counters with Different Modulus by Harnessing IC 74HC163

This paper deals with a numerical investigation using PSPICE, based on the hardware design of digital circuits, which shows a sequential behaviour. There is a large number of ready-state Integrated Circuits (IC) which can be designed by designer requirements, depending on operation cases. Before the manual hardware design, it is very important that the designed hardware is realized in order to simulate software tools, that enable the designer to prove the functionality of the designed circuit in every step during this process. The IC 74HC163 configurations are used for circuit simulation, which can be utilized as counter circuits with different modulus, according to the specific cases of the operation. Using the Computer Aided Design (CAD) systems during designing phase of digital circuits greatly improves the efficiently of digital systems depending on design requirements. The obtained results through the software tools after simulating of the designed circuits help designers to predict the performance of the new design.

A RANDOM COUNTER IN USING SHIFT REGISTER AND ENCODER

Mostly some specific computer circuits and digital circuit applications need a random counter circuit module for handling specific tasks or operations. To design this kind of circuit, it is more common to use the standard format design of synchronous counter, although this will be more complicated to derive its truth table and karnaugh-maps in order to solve the right output equations for flip-flop inputs. This paper will introduce another way of designing a digital random counter, using shift register and encoder, which is easier to applied and the sequence of this counter can be managed randomly. The methodology being used for this research is mainly tounderstand the basic concept and combine the functions of shift register and encoder, to derive a new and simple form of designing a random counter. Using an Electronics Workbench software, the outputs are shown in logic simulation.

Power efficient synchronous counter design

The Performance of any VLSI circuit depends on its design architecture, which optimizes power and provides high reliability. To design any circuit with low power, power optimization of circuit at different levels is needed. Most of the system level architectures consists of sequential circuits, design of these circuits plays an pivotal role in reducing overall power of the system. Counters are basic building blocks in many VLSI applications such as timers, memories, ADCs/DACs, frequency dividers etc. It is observed that design of counters has power overhead because of requirement of high power consumption for the clock signal distribution and undesired activity of flip-flops due to presence of clocks. In this brief, we propose a power efficient design of synchronous counters that reduces the power consumption due to clock distribution for different flip-flops and offers high reliability. The proposed counter design is evaluated and analyzed in terms of power in a standard 45 nm CMOS technology in CADENCE and also evaluated in Synopsys Design Compiler and IC Compiler for ASIC (Application Specific Integrated Circuit) synthesis results. The proposed counter design has lower power requirement and power-area product than existing counter architectures and the power reduction is more significant for wide-bit counters.

High speed and low cost synchronous counter design in quantum-dot cellular automata

Quantum-dot Cellular Automata (QCA) is a very interesting nano-scale technology. Extremely small feature size and ultra-low power consumption are the most important features of QCA compared to CMOS. Counters are considered as one of the most fundamental components in sequential circuits. Previous QCA synchronous counters (QSCs) have been designed and simulated using two methods. In the first method, QSCs utilize direct mapping flip-flop designs in CMOS technology to QCA. In the second method, QSCs are designed with the inherent capability of QCA technology. Despite being attractive, mentioned approaches have constraints (i.e. long wire length and area issues). In this brief, design and simulation of a QSC are presented through combining the two approaches. Experimental results reveal that the novel combination not only overcomes limitations of the above methods, but also improves delay and cost function (at least two times lower than the best previous QSCs).

Neural Network Synchronous Binary Counter Using Hybrid Algorithm Training

Neural Network Synchronous Binary Counter Using Hybrid Algorithm Training

English

English

Robust and efficient quantum-dot cellular automata synchronous counters

The design of a synchronous sequential circuit is a very interesting and challenging research topic in quantum-dot cellular automata (QCA) technology. In this paper, a robust and efficient QCA design of synchronous counters is proposed. Firstly an innovative design of level-sensitive D-type flip–flip (D-FF) and an appropriate “edge-to-level” converter are introduced by utilizing inherent capabilities of QCA implementations. Secondly these efficient elements are used for designing QCA counters with different bit sizes. Simulations using QCADesigner and QCAPro tools are performed to check performance and power of proposed designs. Results indicate the superiority of proposed designs in terms of complexity and power dissipation as compared to their latest counterparts.

How to Teach the Sequential Part of Digital Electronics Basis with Project Pedagogy? Thanks to a Self-Working Card Trick Named “Cyclic Number”

Why use Magic for teaching digital electronics theory and software? Magicians know that, once the surprise has worn off, the audience will seek to understand how the trick works. The aim of every teacher is to interest their students, and a magic trick will lead them to ask how? And why? And how can I create one myself? Whatever the student's professional ambitions, they will be able to see the impact that originality and creativity have when combined with an interest in one's work. The students know how to “perform” a magic trick for their family and friends, a trick that they will be able to explain and so enjoy a certain amount of success. Sharing a mathematical / informatics demonstration not easy and that they do so means that they will have worked on understood and are capable of explaining this knowledge. Isn't this the aim of all teaching? In this article I present a self-working magic card trick, its global study and how, with a project pedagogy, digital electronics can be teached. I have presented, in a previous article in the same journal, all the notions of combinatory digital electronics. In this article I presented how to introduce the flip-flop gates, synchronous and asynchronous counters designed thanks to transition tables without using clear/reset entries of the gates. In order to visualize the results, seven segment displays with the associated encoders and decoders could be introduce and simulated by an open source software named “Logisim”. The truth table of each command circuits of the complete cycle can be calculated by Open Office.

A Fully Differential RC Calibrator for Accurate Cut-off Frequency of a Programmable Channel Selection Filter

A fully differential RC calibrator for accurate cut-off frequency of a programmable channel selection filter is proposed. The proposed RC calibrator consists of an RC timer, clock generator, synchronous counter, digital comparator, and control block. To verify the proposed RC calibrator, a six-order Chebyshev programmable low-pass filter with adjustable 3 dB cut-off frequency, which is controlled by the proposed RC calibrator, was implemented in a 0.18-mm CMOS technology. The channel selection filter with the proposed RC calibrator draws 1.8 mA from a 1.8 V supply voltage and the measured 3 dB cut-off frequencies of the channel selection LPF is controlled accurately by the RC calibrator.

Novel Designs of Quantum Reversible Counters

Reversible logic, as an interesting and important issue, has been widely used in designing combinational and sequential circuits for low-power and high-speed computation. Though a significant number of works have been done on reversible combinational logic, the realization of reversible sequential circuit is still at premature stage. Reversible counter is not only an important part of the sequential circuit but also an essential part of the quantum circuit system. In this paper, we designed two kinds of novel reversible counters. In order to construct counter, the innovative reversible T Flip-flop Gate (TFG), T Flip-flop block (T_FF) and JK flip-flop block (JK_FF) are proposed. Based on the above blocks and some existing reversible gates, the 4-bit binary-coded decimal (BCD) counter and controlled Up/Down synchronous counter are designed. With the help of Verilog hardware description language (Verilog HDL), these counters above have been modeled and confirmed. According to the simulation results, our circuits’ logic structures are validated. Compared to the existing ones in terms of quantum cost (QC), delay (DL) and garbage outputs (GBO), it can be concluded that our designs perform better than the others. There is no doubt that they can be used as a kind of important storage components to be applied in future low-power computing systems.

A Fractional-N Counter-Assisted DPLL With Parallel Sampling ILFD

A fractional-N digital phase-locked loop (DPLL) with ring oscillator based injection-locked frequency divider (ILFD) and parallel sampling phase samplers is presented. The ILFD utilizes dual path injection technique to achieve wide locking range (4.2–23 GHz) and low power consumption. A low-power parallel sampling phase sampler based time-to-digital converter (TDC), which achieves sub-gate-delay resolution by sampling the ILFD’s multi-phase outputs using parallel sampling technique, is proposed. The TDC resolution is determined by delay spacing between successive sampling clocks, which is ensured through digital calibration loops. Due to injection locking, no calibration is required to normalize the TDC step to the DCO output period. A hybrid high speed counter architecture, combining a 2 bit asynchronous counter and a 6 bit synchronous counter, is proposed to achieve high speed (>4 GHz) operation with low power consumption. The proposed design is fabricated in a 65 nm CMOS process and occupies 0.1 mm2. The synthesizer covers 13.6–16.8 GHz output and dissipates 8.5 mW. The measured output phase noise achieves −89 dBc/Hz and −125 dBc/Hz at 100 kHz and 10 MHz offsets, respectively. The measured jitter is less than 0.43 ps.