Abstract
The design of a synchronous sequential circuit is a very interesting and challenging research topic in quantum-dot cellular automata (QCA) technology. In this paper, a robust and efficient QCA design of synchronous counters is proposed. Firstly an innovative design of level-sensitive D-type flip–flip (D-FF) and an appropriate “edge-to-level” converter are introduced by utilizing inherent capabilities of QCA implementations. Secondly these efficient elements are used for designing QCA counters with different bit sizes. Simulations using QCADesigner and QCAPro tools are performed to check performance and power of proposed designs. Results indicate the superiority of proposed designs in terms of complexity and power dissipation as compared to their latest counterparts.
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