Design of efficient binary-coded decimal adder in QCA technology with a regular clocking scheme

Abstract

Quantum-dot cellular automata (QCA) is a promising nanotechnology that offers an alternative to complementary metal-oxide-semiconductor (CMOS) technology. Nanoscale size, ultra-low power dissipation, and Terahertz range operating frequency make QCA more attractive to circuit designers. Recently, numerous designs of QCA have been proposed but aren't practically implementable due to random clocks in the design. In QCA designs, there is a need for proper clocking scheme to favour placement and routing and to facilitate QCA nano-computing synthesis. In this paper, a novel design of Binary-Coded Decimal (BCD) adder, based on QCA technology, with a realistic clocking scheme is presented. System simulations of the proposed designs are performed using QCA designer software Ver. 2.0.3 while power dissipation is investigated using the QCA Pro tool. Besides, in terms of power dissipation, the suggested QCA BCD adder dissipates 2.788 × 10−5 mW, whereas CMOS- based design consume 1.34 mW of power.