Novel ternary D-Flip-Flap-Flop and counter based on successor and predecessor in nanotechnology

Abstract

This paper presents a novel design of ternary circuits using carbon nano-tube transistors (CNTFETs). Using multi-valued logic can reduce chip interconnections, which can have a direct effect on chip area and interconnections power consumption. In this paper, at first, a novel design of ternary successor and predecessor is done with one supply voltage and is compared with the previous design based on CNTFETs. It is shown that this new design provides excellent energy efficiency. Furthermore, a novel structure for the D-Flip-Flap-Flop design is proposed by combining the successor and the predecessor; in this D-Flip-Flap-Flop, the second output is the next level of the first output instead of the invert of that, so this D-F.F.F is easily applicable to the counter design. For the first time, two types of ternary synchronous and asynchronous counters are designed based on CNTFETs, which can be extended to the desired bits using the proposed successor and predecessor on the basis of D-Flip-Flap-Flop. Simulation results using HSPICE software and CNT-32 nm model demonstrate that the proposed ternary circuits (successor, predecessor and D-Flip-Flap-Flop) consume significantly lower power, delay and PDP, as compared with the previous works with one supply voltage; Furthermore, the first designs of ternary synchronous and asynchronous counters based on the CNTFETs can function flawlessly with a high performance.