Switching Energy Research Articles

Investigation of PNN Inverter-Based Low PDP 12T GNRFET Full Adder for VLSI Signal Processing Applications

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16[Formula: see text]nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16[Formula: see text]nm MOS-GNRFET model.

New Approach in Booth Decoder/Encoder and 5-2 Compressor for Multipliers

This paper proposes two novel approaches: a signed–unsigned modified Booth decoder/encoder that is used for the production of partial products and a 5-2 compressor for the addition stage of partial products. The improvement of a circuit can be done at the transistor level and the gate level. To improve the circuits at the gate level for the modified Booth decoder/encoder, a new table was designed and also the 5-2 compressor was obtained by changing the truth table. Speed, power consumption and area were improved in the proposed structures. In this paper, at the transistor level, the gate diffusion input (GDI) technique was used to implement logical gates and the gate-level delay of the GDI structures was also calculated. The results indicated that the proposed 5-2 compressor had a delay of 119 ps with a power consumption of 65[Formula: see text][Formula: see text]W, which shows a 23.5% improvement in power delay product (PDP) compared to the best structure in the comparison table, whereas the proposed Booth decoder/encoder had a delay of 257 ps with a power consumption of 61.74[Formula: see text][Formula: see text]W and shows a 63.7% improvement in PDP compared to previous studies. By using the proposed structures in the multiplier, a 22% improvement in PDP was observed. To simulate the obtained structures, the TSMC 0.18 and 0.09[Formula: see text][Formula: see text]m technologies and the HSPICE software were used. Cadence software was used to implement the layouts of the proposed structures.

Energy-Efficient Design and CNFET Implementation of GDI-Based Ternary Prefix Adders

Abstract Ternary adders have produced more benefits compared to binary adders (i.e.) the ternary adder occupies less amount of area as well as produces less interconnect complexity. However, the CMOS implementation of the ternary adders failed to perform the process when the channel length was taken as 32nm. At 32nm technology, the CMOS transistors exhibit undesired effects such as Short Channel Effects (SCEs), mobility degradation, high leakage current, etc. Multi-gate devices are preferred to overcome these issues. CNFETs (Carbon Nano-tube Field Effect Transistors) are one of the technologies to work efficiently when the channel length is 32nm. In this paper, CNFET-based ternary prefix adders are designed. Power consumption is the most critical requirement for the VLSI system, as it enhances Energy Efficiency and reduces heat dissipation. One way to achieve this power reduction is by minimizing the number of transistors employed in the adder circuits. This study employed a reduction technique known as GDI (Gate Diffusion Input) logic included in the proposed prefix adder design. The overall experimental investigation is done with the help of the HSPICE supporting platform. The proposed adder improved by reducing the power by up to 83%, energy by up to 83%, current by up to 78%, and delay by up to 96%. Finally, the PDP (Power Delay product) was also reduced by 84% compared to existing ternary adders. The proposed design proves to be highly effective in implementing the neuron structure, with the corresponding parameters thoroughly analysed and well-documented in this study.

Twice‐input variable‐resolution single‐side switching scheme without reset energy for SAR ADC

AbstractA twice‐input variable‐resolution single‐side switching scheme without reset energy is proposed for successive approximation register (SAR) analogue‐to‐digital converters (ADCs). The proposed switching scheme is based on semi‐resting DAC technology to design a four‐array architecture capable of handling twice the swing of the signal input while reducing the capacitor array size. The technique of top‐plate sampling and monotonic shift is utilized so that no switching energy is generated for the first three comparisons. The proposed scheme utilizes full‐capacitor split, bridged switch, and C‐2C dummy capacitor technology, which reduces average switching energy consumption by 99.8% compared to conventional schemes and enables ADC variable resolution function, making the SAR ADC more suitable for IoT applications.

Intrinsically Stable Charged Domain Walls in Molecular Ferroelectric Thin Films

AbstractCharged domain walls in ferroelectrics hold great promise for applications in ferroelectric random‐access memory (FeRAM), with advantages such as low energy consumption, high density, and non‐destructive operation. Due to the mechanical compatibility condition, the neutral domain walls are dominant in traditional ferroelectric thin films. Herein, using phase‐field simulations, the formation of intrinsically stable charged domain walls (CDWs) in the molecular ferroelectric films is demonstrated, which can be mainly attributed to the small mechanical stiffness. The switching kinetics are further investigated for the CDWs, showing a lower switching barrier as compared to the neutral counterparts. Moreover, it is indicated that increasing the compressive misfit strain can lead to prolonged switching time, with a significantly increased switching energy barrier. These findings pave the way for the potential applications of metal‐free organic ferroelectric materials in FeRAM devices.

Investigation of Optical Interconnects for nano-scale VLSI applications

The relentless trend toward miniaturization has brought interconnects to the brink of communication bottlenecks, operating at or near their ampacity (current carrying capacity) limits. This degradation in performance necessitates novel technologies with increased ampacity. This study explores optical interconnect (OI) as a potential future technology, offering high-bandwidth communication and low latency. This study models and simulates OI, integrating recent optical device advancements with modest modulator and detector capacitance (50 fF). Performance metrics including signal delay, power dissipation, and power-delay-product (PDP) are compared across copper (Cu) and single-wall carbon nanotube bundle (SWCNT-B) interconnects at 22 nm and 14 nm technology nodes. Results consistently show OI, with an active voltage current feedback (AVCF) based regulated gain cascode (RGC) transimpedance amplifier (TIA) receiver, outperforms Cu and SWCNT-B interconnects at global lengths and beyond. For instance, at 1000 μm and 22 nm, OI exhibits 88.47 % and 62.15 % delay improvements over Cu and SWCNT-B, respectively. This trend persists at 14 nm, with OI showing 93.68 % and 84.29 % delay improvements, respectively. Additionally, OI surpasses Cu and SWCNT-B in power efficiency beyond a critical length. As interconnects extend to global scales and beyond, the differences in delay, power, and PDP between OI and electrical interconnect increases, highlighting OI's advantages for future VLSI IC applications.

A new type of pentagonal structure HgS2 monolayer with abundant active sites and low Gibbs free energy for photocatalytic water splitting

Discovery of new two-dimensional (2D) materials not only has important fundamental research significance but also has promising application prospects. Through systematic structure searching combined with density functional theory calculations and simulations, we predict a new 2D monolayer HgS2 material featuring with a previously unreported type of pentagonal structure with orthorhombic P21212 symmetry. The penta-HgS2 monolayer shows good thermal, thermodynamic, mechanical and dynamic stabilities, exhibiting ferroelastic phase transition with an ultralow switching energy barrier (about 1 meV/atom), high ultimate strength of 12 N/m, moderate indirect band gap of 2.25 eV. In addition, the penta-HgS2 monolayer shows significantly anisotropic carrier mobility with a large anisotropy ratio of 98.5 along the y direction. More importantly, the penta-HgS2 monolayer exhibits abundant catalytic active sites, low Gibbs free energy (ΔGH ranging from 0.656 to 1.687 eV) for hydrogen evolution reactions, excellent solar light absorption capacity (∼105 cm−1) with the solar-to-hydrogen efficiency reaching up to 11.83%. The excellent ultimate tensile ability and the ultralow ferroelastic phase transition energy barrier implies penta-HgS2 monolayer material can be used to manufacture flexible mechanical and nanoelectronic devices. The suitable band edge alignments, ultrahigh carrier mobility anisotropy, high catalytic activity and excellent visible light adsorption performance indicate that penta-HgS2 monolayer is a promising candidate photocatalyst for high-performance photocatalytic water splitting. The present work not only supplements a new member to the 2D pentagonal structure material family, but also points out its promising applications in nanoscale devices and photocatalytic hydrogen productions.

Low Power Multiplier Using Approximate Adder for Error Tolerant Applications

In embedded applications and digital signal processing systems, multipliers are crucial components. In these applications, there is an increasing need for energy-efficient circuits. We use an approximate adder for error tolerance in the computational process to improve performance and reduce power consumption. Due to human perceptual constraints, computational errors do not significantly affect applications like image, audio, and video processing. Adiabatic logic (AL), which recycles energy, can also be used to build circuits that require less energy. In this work, we propose a carry save array multiplier employing an approximate adder based on CMOS logic and clocked CMOS adiabatic logic (CCAL) to conserve power. Additionally, using a precise full adder, multiplier parameters like average power and power delay product are calculated and compared with the multiplier. We performed simulations using 180 nm technology in Cadence Virtuoso.

Sub-picosecond, strain-tunable, polarization-selective optical switching via anisotropic exciton dynamics in quasi-1D ZrSe3

In cutting-edge optical technologies, polarization is a key for encoding and transmitting vast information, highlighting the importance of selectively switching and modulating polarized light. Recently, anisotropic two-dimensional materials have emerged for ultrafast switching of polarization-multiplexed optical signals, but face challenges with low polarization ratios and limited spectral ranges. Here, we apply strain to quasi-one-dimensional layered ZrSe3 to enhance polarization selectivity and tune operational energies in ultrafast all-optical switching. Initially, transient absorption on unstrained ZrSe3 reveals a sub-picosecond switching response in polarization along a specific crystal axis, attributed to shifting-recovery dynamics of an anisotropic exciton. However, its polarization selectivity is weakened by a slow non-excitonic response in the perpendicular polarization. To overcome this limitation, we apply strain to ZrSe3 by bending its flexible substrate. The compressive strain spectrally decouples the excitonic and non-excitonic components, doubling the polarization selectivity of the sub-picosecond switching and tripling it compared to that in the tensile-strained ZrSe3. It also effectively tunes the switching energy at a shift rate of ~93 meV %-1. This strain-tunable switching is repeatable, reversible, and robustly maintains the sub-picosecond operation. First-principles calculations reveal that the strain control is enabled by momentum- and band-dependent modulations of the electronic band structure, causing opposite shifts in the excitonic and non-excitonic transitions. Our findings offer a novel approach for high-performance, wavelength-tunable, polarization-selective ultrafast optical switching.

An energy-efficient 16 MS/s 10-bit SAR ADC with MSB-block switching scheme

An energy-efficient MSB-block switching scheme without common-mode voltage variation for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. Benefit from a pair of extra switches embedded in the capacitive digital-to-analog converter (CDAC), the proposed MSB-block switching scheme can reduce switching energy without further reducing the capacitor unit. The proposed switching scheme can achieve 93.8 % and 49.9 % savings in switching energy compared with the conventional switching scheme and the Vcm-based switching scheme, and the simulated differential-nonlinearity (DNL) and integrated-nonlinearity (INL) are 0.160 and 0.156LSB, respectively. The proposed switching scheme is verified in a 1.2-V 10-bit 16 MS/s SAR ADC in 65 nm CMOS technology. At maximum sampling rate, the proposed SAR ADC achieves an effective number of bits (ENOB) of 9.50 and a power consumption of 103.5μW, leading to a Figure of Merit of 8.93 fJ/Conversion-step.

Realization of a high-efficient GDI-based 4:2 compressor for sum of absolute difference detection in image and signal processing

A new 4:2 approximate compressor is designed based on gate diffusion input (GDI), which has 14 transistors and only 6 errors in its outputs. The integration of the GDI with the dynamic threshold (DT) overcomes the body effect by the selection of carbon nanotube field-effect transistors (CNTFET) technology. By embedding the proposed compressor in the 8-bit sum of absolute difference (SAD) system, an area of 284.6 µm2 is occupied and a reliable system for difference detection between two images and electrocardiogram (ECG) results. Considering the fair conditions of comparison, the proposed circuit has significant performance in terms of circuitry parameters such as power, delay, and figure of merits (FoMs). In terms of power-delay-product (PDP) and power-delay-area-product (PDAP) the proposed cell shows a saving of 27 % and 47 %, respectively. A 40 % improvement in terms of a FoM containing PDP and power signal-to-noise ratio (PSNR) compared to the closest competitor qualifies the proposed circuit over the other counterparts. The proposed cell has a high performance under the difference detection in images and ECGs.

Multiferroicity in a two-dimensional vanadium dioxide

Two-dimensional (2D) multiferroic materials have attracted great interest owing to the integration of ferroelastic and ferromagnetic properties. We identify a novel 2D multiferroic vanadium dioxide (VO₂) monolayer exhibiting a monoclinic phase with a C2/m space group using density functional theory (DFT) calculations. The energetic, dynamic, thermodynamic and mechanical analyses indicate that the monolayer exhibits excellent stability and can be prepared experimentally. The arrangement of the electronic energy bands is analogous to that of a type I heterostructure. The electron doping at a concentration of 0.2 electrons per V atom results in a significant increase in the Curie temperature (TC) from 11.2 to 184 K estimated by Monte Carlo simulations, and a transition from semiconductor to half-metallicity. In addition, the VO₂ monolayer exhibits 120° ferroelastic switching with a moderate switching energy barrier of 32 meV per atom, subsequently allowing 120° rotation of the easy magnetisation axis. Our work reveals the intrinsic multiferroicity of VO₂, which may provide a guidance on the design of next-generation mechanical/spintronic devices.

Experimental Demonstration and Analysis of 3.3kV 4H-SiC Common-Drain Bidirectional Charge-Balanced Power MOSFETs

By using 4H-SiC packaged Charge-Balanced (CB) MOSFET, we have experimentally demonstrated a 3.3kV 4H-SiC common-drain bidirectional (BD) CB power MOSFET and measured its static and dynamic characteristics compared to its unidirectional counterpart. We show that the BD CB MOSFET conducts and blocks at the first and third quadrants with the appropriate gate bias with an on-state resistance double its unidirectional counterpart, while its switching energies are 12 (19) and 34 (12) mJ/cm2 for BD CB MOSFET (UD CB MOSFET).

Thermally tuned on-chip optical memory

Phase-change materials, known as Chalcogenide alloys, are a promising alternative to traditional random-access memory. They possess characteristics that are particularly beneficial for non-volatile storage applications. The features of the Phase change material Ge-Sb-Te alloy (GST) used for substrate-integrated optical memory include scaling, quick switching times, minimal switching energy, and exceptional thermal stability. The material has two tuneable states, amorphous and crystalline, with the amorphous layer for loading data optically. In contrast, the crystalline state holds the data longer without significant loss. The study designed a classic thermally tuned optical memory on a silicon substrate. It demonstrated a dependency of lattice structure on external voltage and revealed a large storage capacity for information in the form of an optical signal. The heat transport simulation utilized the Heat Transport (HEAT) solver of the Finite Element Eigenmode (FEEM) solver. At the same time, the optical response analysis involved the Finite Difference Time Domain (FDTD) solver of Lumerical. The proposed structure exhibits a memory-switching phenomenon when a temperature shift of about 60 °C from room temperature is induced by a change in the external voltage of 147 mV. These findings have substantial implications for non-volatile storage memory development, providing a potential solution for high-capacity, low-energy data storage.

Higher order and optimized symmetric 2D FIR filter design and hardware architecture implementation using CSD-CSE

In this paper, an optimized and high-performance Two-Dimensional (2D) Finite Impulse Response (FIR) filter is designed and hardware architecture is implemented for image processing applications. The higher-order circular symmetric 2D FIR filter is designed using a modified McClellan Transformation called a P4 transformation. The perfect circular symmetry in the contour of the 2D FIR filter and less complexity and error are attained by this proposed P4 Transformation. Next, the designed filter coefficients are represented by the Canonical Signed Digit (CSD) number format to attain the multiplier-less design to avoid the power complexity multipliers. Further, to reduce the hardware complexity, the Common Subexpression Elimination (CSE) technique is utilized to reduce the number of adders and hence area and power are decreased. Each sub-filter corresponding to the CSD coefficient rows is realized and integrated as a 2D FIR filter using a Fully Direct-type architecture. This 2D FIR filter architecture is coded by Verilog and synthesized by Cadence tools in a 45 nm CMOS technology library. The Delay, Power Consumption (PC), and Area reports were generated by the Genus synthesis tool and compared with the state-of-the-art works. The PC, area, and delay of the proposed filter architecture are reduced to the minimum of 13.96%, 69.1%, and 1.4%, respectively when compared to the existing filter architectures. The maximum of 10.48 times and a minimum of 1.18 times of Area Delay Product (ADP), and a maximum of 10.69 times and a minimum of 1.063 times of Power Delay Product (PDP) are smaller than the existing 2D filter architectures.

Design of dual port 9T SRAM cell with parallel processing and high performance computing

Abstract To meet industry requirements of higher transistor count SRAM cells this paper is proposing, a nine-transistor configuration static random access memory (SRAM) cell which is accessible by dual bit line and performing simultaneous read and write operations. The suggested 9T (P9T PS) cell is constructed at 32 nm CMOS and is operating at an operating voltage 0.9 V. To justify the refined performance of proposed design various analysis are carried out that shows the static noise margins (SNM) that occurs while executing the read operation is 0.368 V and hold operation by the cell is 0.364 V, while the write operation has an SNM of 0.422 V. The access time for write and read functions of the cell is found to be 1.2 nS and 4.5 nS respectively. The P9T PS SRAM is compared with other dual-port and single-port 9T SRAM cells is stand out to be pre-eminence in performance in terms of noise immunity, temperature variations, power consumption (static and dynamic both), power delay product (PDP), SNM to PDP and area ratio (SAPR) and electric quality matric. Total leakage power for P9T PS cell is found to be 22.1 nW. The P9T PS bit cell is also found to be power efficient as it is consuming minimal power for all of the operations. Area layout of the P9T (PS) is found to be 22.372 μm2. The results are also supported by the process corner variation analysis for four different corners. LT-spice software is used to carry out all the simulations and analysis.

Ferroelectric Aluminum Scandium Nitride Transistors with Intrinsic Switching Characteristics and Artificial Synaptic Functions for Neuromorphic Computing.

Aluminum Scandium Nitride (Al1-xScxN) has received attention for its exceptional ferroelectric properties, whereas the fundamental mechanism determining its dynamic response and reliability remains elusive. In this work, an unreported nucleation-based polarization switching mechanism in Al0.7Sc0.3N (AlScN) is unveiled, driven by its intrinsic ferroelectricity rooted in the ionic displacement. Fast polarization switching, characterized by a remarkably low characteristic time of 0.00183ps, is captured, and effectively simulated using a nucleation-limited switching (NLS) model, where the profound effect of defects on the nucleation and domain propagation is systematically studied. These findings are further integrated into Monte Carlo simulations to unravel the influence of the activation energy for ferroelectric switching on the distributions of switching thresholds. The long-term reliability of devices is also confirmed by time-dependent dielectric breakdown (TDDB) measurements, and the effect of thickness scaling is discussed. Ferroelectric field-effect transistors (FeFETs) are demonstrated through the integration of AlScN and 2D MoS2 channel, where biological synaptic functions can be emulated with optimized operation voltage. The artificial neural network built from AlScN-based FeFETs achieves 93.8% recognition accuracy of handwritten digits, demonstrating the potential of ferroelectric AlScN in future neuromorphic computing applications.

Investigating the 20T Hybrid Full Adder Design for Low Power and High-Performance Computing

The 1-bit full adder is a crucial building block in digital circuits, widely used in various applications such as arithmetic circuits, digital filters, and computer memory. In this study, a thorough investigation of a novel 1-bit full adder circuits was conducted, covering their design, analysis, and optimization for minimizing their power consumption and delay while maintaining their robustness and functionality. The design also introduces modified XOR and XNOR gates as crucial components. The proposed circuit was simulated using Cadence Virtuoso tool with 90-nm GPDK CMOS technology. To evaluate the proposed adder, comparisons were made with several well-known adder designs based on power consumption, speed, and power delay product. The proposed hybrid full adder improved power delay product by 20.6% to 69.4% and reduced worst-case propagation delay by 16.6% to 63.5% compared to prior designs in the literature. This study's findings offer useful insights into digital circuit design and can contribute to the development of low-power, high-performance full adder circuits.

Picosecond Femtojoule Resistive Switching in Nanoscale VO2 Memristors.

Beyond-Moore computing technologies are expected to provide a sustainable alternative to the von Neumann approach not only due to their down-scaling potential but also via exploiting device-level functional complexity at the lowest possible energy consumption. The dynamics of the Mott transition in correlated electron oxides, such as vanadium dioxide, has been identified as a rich and reliable source of such functional complexity. However, its full potential in high-speed and low-power operation has been largely unexplored. We fabricated nanoscale VO2 devices embedded in a broadband test circuit to study the speed and energy limitations of their resistive switching operation. Our picosecond time-resolution, real-time resistive switching experiments and numerical simulations demonstrate that tunable low-resistance states can be set by the application of 20 ps long, <1.7 V amplitude voltage pulses at 15 ps incubation times and switching energies starting from a few femtojoule. Moreover, we demonstrate that at nanometer-scale device sizes not only the electric field induced insulator-to-metal transition but also the thermal conduction limited metal-to-insulator transition can take place at time scales of 100s of picoseconds. These orders of magnitude breakthroughs can be utilized to design high-speed and low-power dynamical circuits for a plethora of neuromorphic computing applications from pattern recognition to numerical optimization.

Investigation of Dead Time Losses in Inverter Switching Leg Operation: GaN FET vs. MOSFET Comparison

This paper investigates the commutation transients of MOSFET and GaN FET devices in motor drive applications during hard-switching and soft-switching commutations at dead time operation. This study compares the switching behaviors of MOSFETs and GaN FETs, focusing on their performance during dead time in inverter legs for voltage source inverters. Experimental tests at various phase current levels reveal distinct switching characteristics and energy dissipation patterns. A validated simulation model estimates the experimental energy exchanged and dissipated during switching transients. The results demonstrate that GaN FETs exhibit lower overall losses at shorter dead times compared to MOSFETs, despite higher reverse conduction voltage drops. The study provides a quantitative framework for selecting optimal dead times to minimize energy losses, enhancing the efficiency of GaN FET-based inverters in low-voltage motor drive applications. Finally, a dead time optimization strategy is proposed and described.