Abstract
The 1-bit full adder is a crucial building block in digital circuits, widely used in various applications such as arithmetic circuits, digital filters, and computer memory. In this study, a thorough investigation of a novel 1-bit full adder circuits was conducted, covering their design, analysis, and optimization for minimizing their power consumption and delay while maintaining their robustness and functionality. The design also introduces modified XOR and XNOR gates as crucial components. The proposed circuit was simulated using Cadence Virtuoso tool with 90-nm GPDK CMOS technology. To evaluate the proposed adder, comparisons were made with several well-known adder designs based on power consumption, speed, and power delay product. The proposed hybrid full adder improved power delay product by 20.6% to 69.4% and reduced worst-case propagation delay by 16.6% to 63.5% compared to prior designs in the literature. This study's findings offer useful insights into digital circuit design and can contribute to the development of low-power, high-performance full adder circuits.
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