Switch Size Research Articles

Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters

In this work we analysed the stepwise charging technique to find the limits from which it is beneficial in terms of load capacitance and charge–discharge frequency. We included in the analysis practical limitations such as the consumption of auxiliary logic needed to implement the technique and the minimum size of auxiliary switches imposed by the technology. We proposed an ultra-low-power logic block to push these limits and to obtain benefits from this technique in small capacitances. Finally, we proposed to use a stepwise driver in the driving of the gate capacitance of power switches in switched-capacitor (SC) DC–DC converters. We designed and manufactured, in a 130 nm process, a SC DC–DC converter and measured a 29% energy reduction in the gate-drive losses of the converter. This accounts for an improvement of 4% (from 69 to 73%) in the overall converter efficiency.

QPS-r: A cost-effective iterative switching algorithm for input-queued switches

In an input-queued switch, a crossbar schedule, or a matching between the input ports and the output ports needs to be computed in each switching cycle, or time slot. Designing switching algorithms with very low computational complexity, that lead to high throughput and small delay is a challenging problem. There appears to be a fundamental tradeoff between the computational complexity of the switching algorithm and the resultant throughput and delay. Parallel maximal matching algorithms (adapted for switching) appear to have stricken a sweet spot in this tradeoff, and prior work has shown the following performance guarantees. Using maximal matchings in every time slot results in at least 50% switch throughput and order-optimal (i.e., independent of the switch size N) average delay bounds for various traffic arrival processes. On the other hand, their computational complexity can be as low as O(log2N) per port/processor, which is much lower than those of the algorithms such as maximum weighted matching which ensures better throughput performance.In this work, we propose QPS-r, a parallel iterative switching algorithm that has the lowest possible computational complexity: O(1) per port. Using Lyapunov stability analysis, we show that the throughput and delay performance are identical to those of maximal matching algorithm. Although QPS-r builds upon an existing technique called Queue-Proportional Sampling (QPS), in this paper, we provide analytical guarantees on its throughput and delay under i.i.d. traffic as well as a Markovian traffic model which can model many realistic traffic patterns. We also demonstrate that QPS-3 (running 3 iterations) has comparable empirical throughput and delay performances as iSLIP (running log2N iterations), a refined and optimized representative maximal matching algorithm adapted for switching.

Which cognitive functions subserve clustering and switching in category fluency? Generalisations from an extended set of semantic categories using linear mixed-effects modelling.

Clustering and switching are hypothesised to reflect the automatic and controlled components in category fluency, respectively, but how they are associated with cognitive functions has not been fully elucidated, due to several uncertainties. (1) The conventional scoring method that segregates responses by semantic categories could not optimally dissociate the automatic and controlled components. (2) The temporal structure of individual responses, as characterised by mean retrieval time (MRT) and mean switching time (MST), has seldom been analysed alongside the more well-studied variables, cluster size (CS) and number of switches (NS). (3) Most studies examined only one to a few semantic categories, raising concerns of generalisability. This study built upon a distance-based automatic clustering procedure, referred to as temporal-semantic distance procedure, to thoroughly characterise the category fluency performance. Linear mixed-effects (LME) modelling was applied to re-examine the differential associations of clustering and switching with cognitive functions with a sample of 80 university students. Our results revealed that although lexical retrieval speed (LRS) is clearly the determining factor for effective clustering and switching, matrix reasoning and processing speed also have significant roles to play, possibly in the processes of identifying and validating the semantic relationships. Interestingly, total fluency score was accurately predicted by the four clustering/switching indices alone; including the cognitive variables did not significantly improve the prediction. These findings underline the importance of the clustering and switching indices in explaining the category fluency performance and the cognitive demands in category fluency.

A Type-I PLL With Foreground Loop Bandwidth Calibration

A 2.4 GHz type-I phase-locked loop with foreground loop bandwidth calibration is presented. A successive approximation method is presented to calibrate the loop bandwidth by digitally adjusting the switch size of the master-slave sampling filter. This brief is fabricated in 45 nm CMOS technology. Its active area is 0.013 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption is 3.6 mW at 2.4 GHz for a supply of 0.9 V. The integrated jitter over 1 kHz to 100 MHz is 3.6 ps. With the supply voltage of 0.88V~0.92V, the variation of the loop bandwidth is reduced from 18.7% to 4.6% by using the loop bandwidth calibration.

Characteristics and mechanism of all-optical switching based on a one-dimensional two-connected periodic triangle optical waveguide network.

In this study, an all-optical switch is designed using a one-dimensional two-segment-connected periodic triangular optical waveguide network, and its switching characteristics and mechanism are investigated. The performance of the switch is numerically calculated by using the network equation and the generalized eigenfunction method and we find it relatively excellent. Its switching efficiency ratio reached 3.7202×1016, which is 5 orders of magnitude larger than the best reported result. The switching threshold control energy is approximately 1.8×10-20J, which is 1 order of magnitude larger than the best reported result. The switch size is approximately 0.0672µm2 and the integration degree is up to 14per/µm2, and it can be used for micrometer chip integration. The switching time is close to 209 fs, which is the same order of magnitude as the previously reported results. In addition, the all-optical switching designed in this study not only exhibits excellent switching performance and a novel working mechanism, but also provides a new technology for the design of pump-free all-optical switching devices.

Size coding of alternative responses is sufficient to induce a potentiation effect with manipulable objects

The mere perception of manipulable objects usually grasped with a power-grip (e.g., an apple) or a precision-grip (e.g., a cherry) potentiate power-grip- and precision-grip-responses, respectively. This effect is seen as to be driven by automatic access of the representation of manipulable objects that includes a motor representation of usually performed grasping behaviors (i.e., the embodied view). Nevertheless, a competing account argues that this effect could be due to an overlapping of size codes used to represent both manipulable objects and response options. Indeed, objects usually grasped with a power- and a precision-grip (e.g., an apple vs. a cherry) could be coded as large- and small-objects, respectively; and power- and precision-grip responses as large- and small-responses, respectively. We conducted 4 experiments to test this hypothesis. In Experiment 1, the response device usually used in studies reporting a potentiation effect is fixed horizontally (the grasping component of responses was removed). We instructed participants to press the small-switch with their index-digit and the large-switch with their palm-hand. In line with the size-coding-hypothesis, responses on the small-switch performed with the index-digit led to shorter RTs when objects usually associated with a precision-grip (e.g., a cherry) were presented compared to objects usually associated with a power-grip (e.g., an apple). A reverse pattern was obtained for responses on the large-switch performed with the palm-hand. In Experiments 2, 3 and 4, we went further by investigating which factors of Experiment 1 allow the size coding of responses: the size of switch and/or the size of the effector part used. Data confirmed the critical involvement of the size of switches and the possible involvement of the size of the effector part used. Thus, data support the possibility that the potentiation of grasping is due to a compatibility/incompatibility between size codes rather than involving motor representations of usually performed grasping behaviors as advocated in several embodied views. Moreover, data support the possibility that responses are coded thanks to a size code that extends the Theory of Event Coding.

Capacitor and Switch Size Comparisons on High-Power Medium-Voltage DC–DC Converters With Three-Phase Medium-Frequency Transformer

This article compares the capacitor requirement of selected isolated dc-dc converters for high-power and medium-voltage applications. A numerical comparison is made for a range of switching frequencies and transition times, considering not only the submodule capacitors of the converters but also the dc-link capacitors. Likewise, a comparison regarding the semiconductor requirement is performed for the converters. Selected inverter topologies to form the dual-active-bridge (DAB) dc-dc converter include the two-level converter (2LC), the modular multilevel converter (MMC), the transition arm converter (TAC), the modular TAC (MTAC), and the controlled transition bridge (CTB) converter. The results show that conventional DAB requires the minimum capacitor size among the converters. Moreover, in the appropriate operation region, the MTAC-DAB and the CTB-DAB provide the possibility of up to 40% and 60% reductions in the amount of required energy storage compared with the MMC-DAB, respectively. It is also shown that the size of the dc-link capacitors becomes comparable with the chain-links' capacitors when the percentage of the transition times per period is reduced to be below 5%. The comparison regarding the semiconductor requirement revealed that the MMC-DAB requires the smallest installed switch power among the multilevel converters.

Parallel Modular Scheduler Design for Clos Switches in Optical Data Center Networks

As data centers enter the exascale computing era, the traffic exchanged between internal network nodes, increases exponentially. Optical networking is an attractive solution to deliver the high capacity, low latency, and scalable interconnection needed. Among other switching methods, packet switching is particularly interesting as it can be widely deployed in the network to handle rapidly-changing traffic of arbitrary size. Nanosecond-reconfigurable photonic integrated switch fabrics, built as multi-stage architectures such as the Clos network, are key enablers to scalable packet switching. However, the accompanying control plane needs to also operate on packet timescales. Designing a central scheduler, to control an optical packet switch in nanoseconds, presents a challenge especially as the switch size increases. To this end, we present a highly-parallel, modular scheduler design for Clos switches along with a proposed routing scheme to enable nanosecond scalable scheduling. We synthesize our scheduler as an application-specific integrated circuit (ASIC) and demonstrate scaling to a 256 × 256 size with an ultra-low scheduling delay of only 6.0 ns. In a cycle-accurate rack-scale network emulation, for this switch size, we show a minimum end-to-end latency of 30.8 ns and maintain nanosecond average latency up to 80% of input traffic load. We achieve zero packet loss and short-tailed packet latency distributions for all traffic loads and switch sizes. Our work is compared to state-of-the-art optical switches, in terms of scheduling delay, packet latency, and switch throughput.

Numerical Investigation of Magnetic Field in AMF Vacuum Arc Switch With Transverse Magnetic Field From Three-Phase Structure

When short current is interrupted in three-phase vacuum interrupter in switchgear, the “U”-type loop composed of external busbar, conductive rod, and vacuum interrupter, and its adjacent phases will generate external actual transverse magnetic field (EATMF) in the interrupter. The existence of EATMF will deflect the vacuum arc, which will affect the breaking performance of vacuum switch. In view of this situation, this article establishes two kinds of electrode system simulation models considering and not considering EATMF. The simulation results show that EATMF is not uniformly distributed in the interelectrode region, but is stronger in the contact cup edge area outside the “U”-type loop, weaker in the “U”-type loop, and mainly affects <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${B} _{x}$ </tex-math></inline-formula> . In different short-circuit cases, EATMF is also different due to the difference of phase distance and short current. In the case of three-phase short circuit, the magnetic field in the interelectrode region of the middle phase is most significantly affected by EATMF. EATMF is closely related to the structure size of vacuum switch. By changing the structure size of vacuum switch (e.g., phase spacing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${d}$ </tex-math></inline-formula> , conductive rod length <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${h} _{1}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${h} _{2}$ </tex-math></inline-formula> ), EATMF can be weakened to some extent.

A Reconfigurable and Extendable Single-Inductor Single-Path Three-Switch Converter for Indoor Photovoltaic Energy Harvesting

This article proposes a single-path three-switch (1P3S) single-inductor dual-input dual-output (SIDIDO) converter to manage power among a photovoltaic (PV) module, battery, and load for indoor PV energy harvesting. For low duty-cycle applications, the 1P3S converter increases efficiency in the PV-to-battery-to-load path by eliminating inductor-sharing power switches. This article also proposes a reconfigurable controller to achieve reconfigurability and extendibility that the 1P3S converter can be reconfigured as a dual-path three-switch (2P3S) SIDIDO converter, combined as a dual-path six-switch (2P6S) SIDIDO converter, or extended as a paralleled-1P3S converter for high energy efficiency in various applications with different PV and load power profiles. To identify each converter’s advantageous applications, the efficiencies of the 1P3S, reconfigured 2P3S, and combined 2P6S converters were analyzed under dynamic PV and load powers. The chip is fabricated in the 0.5- $\mu \text{m}$ CMOS process with a 1.24-mm2 chip area. The measured peak efficiencies for the 1P3S, 2P3S, and 2P6S converters are 95.0%, 95.2%, and 90.0%, respectively, while the measured quiescent currents are 210, 130, and 140 nA, respectively. Compared with the state-of-the-art 2P3S and 2P6S converters, the reconfigured 2P3S and combined 2P6S converters with the proposed IC, respectively, achieve higher efficiency through appropriate switch sizes and ON-time optimizations.

A Design of Wide-Range and Low Phase Noise Linear Transconductance VCO with 193.76 dBc/Hz FoMT for mm-Wave 5G Transceivers

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

An adaptive, fault tolerant, flow-level routing scheme for data center networks

Recent Data center network topologies put forward multiple paths between the end hosts to provide high bisection bandwidth. For the sake of utilizing the multiple paths efficiently many load-balancing techniques are proposed in literature. These load-balancing proposals mainly deal with distribution of traffic among multiple paths. Further, a good load-balancing technique scales down the latency of flows. While balancing the traffic among multiple paths, few proposals also take care of congestion. Flow-level solutions avoid flow splitting to prevent the packet re-ordering at the destination. Such adaptive solutions try to re-route (change the path) flows dynamically based on the feedback received from the network. In case of link failures, re-routing of the flow based on the queue size of the remote switch alone may be sub-optimal. The path to be chosen among multiple paths for re-routing, also poses a valid question. This paper proposes FlowFurl, an adaptive, distributed, end host driven and flow-level load-balancing technique. This adaptive routing technique supports dynamic flow-to-path assignment. This flow-to-path assignment is performed not only based on the congestion at the switch, but also the status of the links along the path. FlowFurl is the first technique to combine link failure and congestion information parameter for re-routing of flows. The proposed technique is deployment friendly, however it incurs small amount of overhead (small amount of memory at each switch to maintain the link state). We show that our proposed scheme FlowFurl performs better than considered schemes in terms of average flow latency, percentage of flows that achieve deadline and average flow throughput, by utilizing local information such as connectivity information with congestion information.

Design of Optical Tunnel Switching Networks for Big Data Applications

In this paper, we proposed large-scale optical tunnel switching networks based on the Torus topology network with WSS (Wavelength Selective Switch) for future big data applications. All nodes of the large-scale optical tunnel switching networks use WSS switch modules, and the communications between nodes use multiple λs (wavelengths), where a tunnel is established with a wavelength which can be reused. The widely used MEMS (Micro-Electro-Mechanical Systems) and LCoS (Liquid Crystal on Silicon) technologies are all millisecond-level switching speeds, so the frame size of the optical frame switch is very large, and this will reduce switching performance. Therefore, they are only suitable for optical tunnel switching networks design, but are not suitable for optical frame switch design. This multi-plane Torus topology network architecture not only increases network throughput, but also has fault tolerance to increase network reliability. When the traffic is changed, the number of tunnels between nodes can be scheduled in time to balance the load traffic and avoid traffic loss. Therefore, it can not only schedule the number of tunnels in time to balance the load traffic, in order to avoid traffic loss, but also because the channel is fixedly established, this does not generate any buffer delay, and this because of the transmission using optical transmission unlimited speed, so it is a good choice for future big data applications that require high speed, high bandwidth and low latency.

Development of an Efficient Router Based on Network on Chip Network

A reconfigurable VLSI architecture for router is the main solution for communication interface quality of service go flexibility of network, cost of chip .The proposed architecture dynamically configure itself with respect to hardware modules such as packet based switch, router and data packet size by changing the conditions of communication and it's requirement at run time .In network on chip were using extended XY algorithm to improve performance of communication. The proposed design work avoids the dead lock and data loss in the path with the help of this design we can achieve high Data through put and low latency .in this paper we are receiving the previous method and approaches of dynamic reconfigurable router in network on chip

Verbal fluency in Alzheimer's disease and mild cognitive impairment in individuals with low educational level and its relationship with reading and writing habits.

ABSTRACT.Verbal fluency (VF) has contributed to building cognitive maps as well as differentiating healthy populations from those with dementia.Objectives: To compare the performance of healthy controls and patients with mild cognitive impairment (MCI) and Alzheimer’s disease (AD) in two semantic VF tasks (animals/clothes) and a phonemic VF task (letter P). Also, to analyze the relationship between the frequency of reading and writing habits (FRWH) and VF in individuals with low educational level.Methods: Sixty-seven older adults aged 60-80 years and with 2-8 years of schooling were divided into three groups: controls (n=25), older adults with MCI (n=24), and older adults with AD (n=18). We analyzed the type, mean size, and number of clusters, switches, intersections, and returns. A post-hoc single-factor ANOVA analysis was conducted to verify differences between groups.Results: Total words in the phonemic VF and the animal category discriminated the three groups. Regarding the animal category, AD patients performed worse than controls in the total number of words, taxonomic clusters, returns, and number of words remembered. We found a moderate correlation between FRWH and total number of words in the phonemic fluency.Conclusions: Semantic (animate) and phonemic (total words) VF differentiated controls and clinical groups from each other - the phonemic component was more related to FRWH than the semantic one. The phonemic VF seems to be more related to cognitive reserve. VF tasks, considering total words and cluster analyses, are a valuable tool to test healthy and cognitively impaired older adults who have a low educational level.

Performance Assessment of Modular Multilevel Half Bridge Inverter for High Power PV Application

This paper presents three-level Modular Multilevel Half Bridge Inverter to achieve lower total harmonic distortion and improved efficiency. Compared to conventional inverter, multilevel inverters provide output voltage of high quality and current waveform while using the low switching frequency. The use of multilevel inverters reduces the switching losses, size of semiconductor switches and the number of harmonic filters as compared to the traditional DC-AC inverters. This paper investigates different classification of multilevel inverters suitable for photovoltaic applications of high power based on efficiency and THD of the output line voltage and current waveform. Multilevel Inverter topologies are simulated as the same environment using MATLAB/Simulink.

Cerebral correlates of switching during verbal fluency task and its impairment in depression: A surface-based morphometry study

Background Major depressive disorder (MDD) is a highly disabling disease of which is related to chronic course. Currently, there is no robust prognosis biomarker. Cognitive dysfunction associated with the disease has been shown to predict treatment outcome. However, its cerebral substrate is poorly known. Verbal fluency (VF), which are broadly used neuropsychological test, assess the production of words according to a required criterion within a constrained time frame. During this task, subjects produce words within subcategories or “clusters” and occasionally “switch” to other clusters. The measurement of the cluster size and number of switches are relevant cognitive markers. Deep learning-based computational analysis method have been shown to improve the reproducibility and scalability of this measurement. The main objective of the current study was to characterize the cortical thickness (CT) surface-based morphometry (SBM) correlates of the switching and clustering scores in patients with MDD using an artificial intelligence empowered speech analysis system. The secondary objective was to compare those cognitive scores with the ones of the control group. Method The study included 26 depressed women and 25 matched in age and education level healthy females’ controls. All subjects underwent VF tests and had a structural Magnetic Resonance Imaging (MRI). The clustering and switching scores were assessed using the computational analysis method introduced by Linz et al ( https://ki-elements.de ). SBM was performed using SPM and CAT12 toolbox. Results In the depressed group, we observed a positive correlation between the switching score in semantic VF test and the CT, in few cortical areas. The main significant correlation was found in the left lingual gyrus (P = 0.003). The switching scores were lower in the depressed group in each VF task (P = 0.019 and P = 0.007). There was no difference between the two groups concerning the cluster size. Conclusion Our study revealed the relationship existing between the number of switches produced by depressed subjects in a semantic VF task and the CT in prefrontal regions and in more posterior areas. These results possibly suggest that switching and clustering scores assessment in VF tasks, and its cerebral correlates, may constitute potential prognosis biomarkers for depression. Although much work is still required, the establishment of such biomarkers has substantial implications for reducing the burden of the disease.

A buck converter based on dual mode asynchronous pulse width modulator

This paper presents a buck type DC-DC converter based on an asynchronous pulse width modulator (APWM). The proposed APWM is a self-oscillating circuitry which is composed of a binary comparator (BAPWM) and a distinctive digitally controlled delay cell. The oscillating frequency of the BAPWM can be tuned by the delay of the modulator loop. By increasing the delay of the modulator loop, the switching frequency decreases and the BAPWM can be reconfigured as a low frequency APWM (LFAPWM) modulator to meet the efficiency requirement at light loads. Also, to save the switching power consumption the high-side power switch size is scaled according to the load conditions. Since the carrier signal is internally generated by the APWM itself, there is no major concern about the ramp signal discontinuity which is make duty cycle disturbance. In addition to, from the point of view of the output spectrum, the proposed converter provides a better performance compared to the conventional PWM (CPWM) and PFM due to its noise shaping property. The proposed converter is designed and simulated in a 0.13-µm CMOS technology to convert an input voltage of 5 V to the output voltage of 2.5 V with the maximum load current of 1 A. The conversion efficiency with full loading range for the 2.5 V output voltage is higher than 85% whereas the peak efficiency is about 92%.

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips

The Network-on-Chips is a promising candidate for addressing communication bottlenecks in many-core processors and neural network processors. In this work, we consider the generalized fault-tolerance topology generation problem, where the link or switch failures can happen, for application-specific network-on-chips (ASNoC). With a user-defined number, K, we propose an integer linear programming (ILP) based method to generate ASNoC topologies, which can tolerate at most K faults in switches or links. Given the communication requirements between cores and their floorplan, we first propose a convex-cost-flow based method to solve a core mapping problem for building connections between the cores and switches. Second, an ILP based method is proposed to allocate K+1 switch-disjoint routing paths for every communication flow between the cores. Finally, to reduce switch sizes, we propose sharing the switch ports for the connections between the cores and switches and formulate the port sharing problem as a clique-partitioning problem Additionally, we propose an ILP-based method to simultaneously solve the core mapping and routing path allocation problems when considering physical link failures only. Experimental results show that the power consumptions of fault-tolerance topologies increase almost linearly with K because of the routing path redundancy. When both switch faults and link faults are considered, port sharing can reduce the average power consumption of fault-tolerance topologies with K = 1, K = 2 and K = 3 by 18.08%, 28.88%, and 34.20%, respectively. When considering only the physical link faults, the experimental results show that compared to the FTTG algorithm, the proposed method reduces power consumption and hop count by 10.58% and 6.25%, respectively; compared to the DBG based method, the proposed method reduces power consumption and hop count by 21.72% and 9.35%, respectively.

Exploitation of wavelength, hardware, and path redundancies in fault-tolerant all-optical DCNs

Abstract Data center performance is affected by three main factors; bandwidth, latency, and reliability of intra-data center interconnection network. Bandwidth and latency are definitely improved by adopting optical technology for intra-data center communication, but fault tolerance of the corresponding optical networks has been raised less. Recently, we introduced two Torus-based, all-optical, and non-blocking networks, i.e. O-TF and O-FTF, addressing reliability of optical networks, and now, in this paper, to address the scalability problem, we propose a novel Optical Clos-based architecture which reduces minimum number of required wavelength channels, as well as, the switch size in each node. Moreover, we examine three different types of redundancies; including (a) wavelength (adopted in O-TF network), (b) hardware (adopted in O-FTF network), and (c) path (adopted Optical Clos)) redundancies, in terms of throughput drop under failures, implementation cost, optical power loss, electrical power, latency, topology, and wiring complexity. In addition to simulating networks utilizing generated traffic based on Microsoft data, realistic traffic has also been considered. Our simulation results confirm that in addition to improving power consumption and latency, O-TF, O-FTF, and O-Clos architectures lead to throughput increment up to 80%, 90%, and 70%, respectively, comparing to WaveCube at the presence of network failure, as result of adopting our proposed fault-tolerant method, named as RAOP.