Switch Size Research Articles

Packet loss and delay performance of feedback and feed-forward arrayed-waveguide gratings-based optical packet switches with WDM inputs-outputs

This paper analyzes the packet loss and delay performance of an arrayed-waveguide-grating-based (AWG) optical packet switch developed within the EPSRC-funded project WASPNET (wavelength switched packet network). Two node designs are proposed based on feedback and feed-forward strategies, using sharing among multiple wavelengths to assist in contention resolution. The feedback configuration allows packet priority routing at the expense of using a larger AWG. An analytical framework has been established to compute the packet loss probability and delay under Bernoulli traffic, justified by simulation. A packet loss probability of less than 10/sup -9/ was obtained with a buffer depth per wavelength of 10 for a switch size of 16 inputs-outputs, four wavelengths per input at a uniform Bernoulli traffic load of 0.8 per wavelength. The mean delay is less than 0.5 timeslots at the same buffer depth per wavelength.

Throughput-enhanced parallel scheduling algorithmfor MIQ switch with moderate number of queues

A novel parallel scheduling algorithm known as the parallel solitary-request-first (PSRF) algorithm is proposed to improve the throughput performance of a multiple input-queued (MIQ) switch when the number of queues is less than the switch size.

The UniMIN switch architecture for large-scale ATM switches

A general expansion architecture is proposed that can be used in building large-scale switches using any type of asynchronous transfer mode (ATM) switch. The proposed universal multistage interconnection network (UniMIN) switch is composed of a buffered distribution network (DN) and a column of output switch modules (OSMs), which can be any type of ATM switch. ATM cells are routed to their destination using a two-level routing strategy. The DN provides each incoming cell with a self-routing path to the destined OSM, which is the switch module containing the destination output port. Further routing to the destined output port is performed by the destination OSM. Use of the channel grouping technique yields excellent delay/throughput performance in the DN, and the virtual FIFO concept is used for implementing the output buffers of the distribution module without internal speedup. We also propose a "fair virtual FIFO" to provide fairness between input links while preserving cell sequence. The distribution network is composed of one kind of distribution module which has the same size as the OSM, regardless of the overall switch size N. This gives good modular scalability in the UniMIN switch. Performance analysis for uniform traffic and hot-spot traffic shows that a negligible delay and cell loss ratio in the DN can be achieved with a small buffer size, and that DN yields robust performance even with hot-spot traffic. In addition, a fairness property of the proposed fair virtual FIFO is shown by a simulation study.

Wavelength-routed optical networks: linear formulation, resource budgeting tradeoffs, and a reconfiguration study

We present algorithms for the design of optimal virtual topologies embedded on wide-area wavelength-routed optical networks. The physical network architecture employs wavelength-conversion-enabled wavelength-routing switches (WRS) at the routing nodes, which allow the establishment of circuit-switched all-optical wavelength-division multiplexed (WDM) channels, called lightpaths. We assume packet-based traffic in the network, such that a packet travelling from its source to its destination may have to multihop through one or more such lightpaths. We present an exact integer linear programming (ILP) formulation for the complete virtual topology design, including choice of the constituent lightpaths, routes for these lightpaths, and intensity of packet flows through these lightpaths. By minimizing the average packet hop distance in our objective function and by relaxing the wavelength-continuity constraints, we demonstrate that the entire optical network design problem can be considerably simplified and made computationally tractable. Although an ILP may take an exponential amount of time to obtain an exact optimal solution, we demonstrate that terminating the optimization within the first few iterations of the branch-and-bound method provides high-quality solutions. We ran experiments using the CPLEX optimization package on the NSFNET topology, a subset of the PACBELL network topology, as well as a third random topology to substantiate this conjecture. Minimizing the average packet hop distance is equivalent to maximizing the total network throughput under balanced flows through the lightpaths. The problem formulation can be used to design a balanced network, such that the utilizations of both transceivers and wavelengths in the network are maximized, thus reducing the cost of the network equipment. We analyze the trade-offs in budgeting of resources (transceivers and switch sizes) in the optical network, and demonstrate how an improperly designed network may have low utilization of any one of these resources. We also use the problem formulation to provide a reconfiguration methodology in order to adapt the virtual topology to changing traffic conditions.

A refined model for performance analysis of output-buffered Banyan networks

In this paper, a new analytical model for performance analysis of output-buffered Banyan networks is proposed. In this model, we consider not only the number of packets stored in a buffer, but also the state of the buffer's Head of Line (HOL) packet ("new" or "blocked"). Simulations are used to verify the model's accuracy. The analytical results show that the maximum throughput decreases when the switch size increases, and that the throughput increases as the buffer size increases. When the buffer size is large enough, say 10, the maximum throughput is close to saturation. The maximum normalized delay increases almost linearly with the increase in buffer size.

Survey of Architectures and Performance of ATM Switches Based on Deflection Routing

AbstractATM switch architectures based on deflection routing are here examined, described in terms of a general switch model and compared with regards to their internal operations. Their common feature is the availability of multiple I/O paths through a multistage unbuffered interconnection network where conflicts for the same interstage link are dealt with by deflecting packets onto the wrong path. The main engineering parameter of the architecture, that is the number of network stages that provides a given packet loss performance is studied in depth. In particular it is found that basically all the examined architectures have a complexity on the order of N log2 N in the range of switch size of usual interest. Furthermore it has been possible to rank the architectures with comparable complexity based on the loss performance they provide. The Shuffleout switch turns out to behave better than other architectures previously known as providing an optimal performance.

A split input sunshine switch architecture

We present the split input sunshine switch, a new ATM switch architecture based on the sunshine switch, which utilizes two distinct input fabrics, primary and secondary, within a sunshine switch architecture. The primary input fabric is sized at the desired size, N/spl times/N, and the secondary switch is sized at N/z /spl times/ N/z, where z is a non-zero power of two. The introduction of the secondary input fabric allows a portion of the primary input fabric's input lines to be used to handle recirculating cells. For medium and large switch sizes, the hardware requirements of this new architecture is shown to be less than that of the original sunshine design for the same quality of service. Computer simulations have been performed on the sunshine switch and the split input sunshine switch in order to select design parameters and compare performance.

On the speedup required for work-conserving crossbar switches

This paper describes the architecture for a work-conserving server using a combined I/O-buffered crossbar switch. The switch employs a novel algorithm based on output occupancy, the lowest occupancy output first algorithm (LOOFA), and a speedup of only two. A work-conserving switch provides the same throughput performance as an output-buffered switch. The work-conserving property of the switch is independent of the switch size and input traffic pattern. We also present a suite of algorithms that can be used in combination with LOOFA. These algorithms determine the fairness and delay properties of the switch. We also describe a mechanism to provide delay bounds for real-time traffic using LOOFA. These delay bounds are achievable without requiring output-buffered switch emulation.

An analytical model for the performance of buffered multicast banyan networks

Banyan networks have been used for the interconnection of processors in scalable parallel computers and have been proposed for use in ATM high-speed communications networks. This article addresses the performance issues of supporting multicast communication in banyan networks. Multicast is the ability to transmit information from a single source node to multiple selected destination nodes in a network. Current trends in networking applications indicate that there will be an increasing demand in future networks for multicast communication. Previous work on the performance of banyan networks has been primarily for the networks which can support only unicast communication. In this article, we present an analytical model for the performance of buffered banyan networks which support multicast communication. Our model indicates that the throughput of a multicast banyan network is generally higher than that of a unicast banyan network. We also discuss the effect of network design parameters such as buffer length and switch size on network performance. Our results, expressed in terms of throughput, packet transfer time and packet loss probability, outline the performance of buffered multicast banyan networks.

Interconnection network organization and its impact on performance and cost in shared memory multiprocessors

Interconnection network organization has a significant impact on multiprocessor system performance. However, detailed and comprehensive studies of the performance and the effect of different organizations are virtually non-existent. In this study, three interconnection network organizations are evaluated as part of a cache-based shared memory multiprocessor system: tori, multistage and single-stage shuffle-exchange networks. A system size is limited to 256 or fewer processors, a range where wiring constraints can be largely ignored. The performance impact of topology choice and switch size and channel width are studied under three different constraints: fixed switch size and channel width, constant number of switch pins, and constant network cost. The cost model reflects switch size and channel width. We find that after a certain point the performance advantage of wider channels becomes small, and the network topology and switch size become the determining parameters. Our results show that the multistage network is the best network topology if cost is not the main limiting factor. Otherwise, the single-stage network is the most cost-effective network topology. 2-D torus networks are seriously limited in terms of performance and cost. The dimension of torus networks needs to be larger than 2 in order to have a reasonable relative performance vis-à-vis networks of other topologies.

A high-performance two-stage packet switch architecture

This paper contributes a distributed packet controller which reduces queueing to a single stage in two-stage packet switches. Software and neural network based controllers are described. Simulations under a range of traffic conditions for a 1024/spl times/1024 switch size shows the simplest architecture has the best performance.

Design of High-Performance Latching Typle Single-Mode Fiber Switches and Theri Characteristice

This paper describes the optical, mechanical, and magnetic design of compact latching type single-mode fiber switches and demonstrates their characteristics including several reliability tests.To reduce the switch size and power, we designed a simple electro-magnetic driving mechanism composed of a solenoid coil and magnets that can move an ultra-light micro-magnetic-alloy pipe fixed on a movable fiber. Insertion loss and reflected light were reduced by injecting refractive- index-matching oil into the switches. We investigated precise optical coupling condition between a movable fiber and stationary fiber in terms of magnetic attraction forces.The fabricated 1×2 switches exhibited a low insertion loss of 0.31dB, a high return loss of 51dB, a relatively fast switching time of <2ms, and low driving power of 9mW. When subjected to endurance (108 switchings), heat cycle, shock and vibration, and long-term (6.5years) intermittent operating tests, they revealed no significant optical or mechanical degradation.

Analysis of interferometric crosstalk in optical switch blocks using moment generating functions

A detailed statistical model describing the detection process in case of interferometric crosstalk is derived. The complexity of the model is independent of the number of crosstalk channels, opposite to the complexity of a modified Gaussian approximation that increases with the number of crosstalk channels. Using our new model, we analyze crosstalk induced power penalty in optical switch blocks as a function of switch size, crosstalk levels and receiver decision thresholds.

Interlake variation in growth and size structure of bluegill (Lepomis macrochirus): inverse analysis of an individual-based model

Habitat structure alters food availability and predation risk, thereby directly affecting growth, mortality, and size structure of fish populations. Size structure has often been used to infer patterns of resource abundance and predation. However, food availability and predation risk in contrasting habitats have proven difficult to measure in the field. We use an inverse modeling approach to estimate food availability and habitat choice parameters from changes in length distributions of bluegill (Lepomis macrochirus). The model suggests that dynamics of bluegill length distributions primarily reflect food availability and habitat choice. Bluegill behavior minimized effects of size-selective predation on size structure. Parameters for food availability and habitat choice were correlated. It was therefore not possible to attain unique estimates of food availability and habitat selection when both were free parameters. However, when one parameter was estimated independently, the other could be identified. In five Wisconsin lakes, seining studies were used to estimate the size at which bluegill switched from littoral to pelagic habitats. Using this measure of switch size in the model, we estimated food availability for bluegill in each lake. These estimates were positively correlated with observed growth (r2 = 0.91), demonstrating the model's ability to estimate food availability.

A prototype broadcast-and-select photonic ATM switch with a WDM output buffer

A rack-mounted prototype of a broadcast-and-select (B and S) photonic ATM switch is fabricated. This switch has an optical output buffer utilizing wavelength division multiplexed (WDM) signals. The WDM technology solves. The cell-collision problem in a broadcast-and-select network and leads to a simple network architecture and the broadcast/multicast function. The prototype can handle 10-Gb/s nonreturn-to-zero (NRZ) coded cells and 5-Gb/s Manchester-coded cells and has a switch size of four. In this prototype, the level and timing design are key issues. Cell-by-cell level fluctuation is overcome by minimizing the loss difference between the optical paths and adopting a differential receiver capable of auto-thresholding. The temperature control of delay lines was successful in maintaining the phase synchronization. Using these techniques, we are able to provide a WDM highway with a bit error rate of less than 10/sup -12/. Fundamental photonic ATM switching functions, such as optical buffering and fast wavelength-channel selection, are achieved. We show our experimental results and demonstrate the high performance and stable operation of a photonic ATM switch for use in high-speed optical switching systems as an interconnect switch for a modular ATM switch and an ATM cross-connect switch.

Layered switch architectures for high-capacity optical transport networks

We propose and analyze layered switch architectures that possess high design flexibility, greatly reduced switch size, and high expandability. The improvement in loss and crosstalk due to the reduced switch size is also discussed. Theoretical models have been developed to compute the network blocking probability using these architectures. Low blocking probability and high network utilization are achieved because of the capability of communication between layers in adjacent switches. The results show that the proposed layered switch architectures are very attractive for high-capacity optical transport networks.

Throughput analysis for input-buffered ATM switcheswithmultiple FIFO queues per input port

Using two different packet scheduling policies, the maximum throughputs of an input-buffered ATM switch with m-FIFO queues per input port are derived when the switch size is large.

Design and performance of a multiple parallel shared memory switch

A new ATM switch architecture is presented. This switch is based on multiple parallel shared memory switches (8×8) which are connected together in a Banyan interconnection network. The parallel shared memory switch (PSMS) is capable of achieving 100% throughput under bursty traffic. This switch has the advantage of requiring a small queue size as in other types of shared memory switches. In contrast to other shared memory, there is no constraint on the switch size implementation since it does not require a speed-up which depends on the size of the switch. Speed-up is needed in the parallel shared memory switch to maintain the sequence of cells, but at a small value dependent on the size of the parallel shared memory switch element (8 in this design). The parallel shared memory switch element is based on distributed shared memory where each memory queue stores cells coming from all inputs. This limits the performance degradation that may occur in a completely shared memory where long streams from a few inputs may unfairly hog the entire space. Analysis and simulation of the switch demonstrates a high performance in terms of end-to-end delay, throughput and cell loss probability.

Design and implementation of Abacus switch: a scalable multicast ATM switch

Describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32/spl times/32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 /spl mu/m CMOS technology and tested to operate correctly at 240 MHz.

An ATM routing and concentration chip for a scalable multicast ATM switch

We have proposed a new architecture for building a scalable multicast ATM switch from a few tens to a few thousands of input/output ports. The switch, called the Abacus switch, employs input and output buffering schemes. Cell replication, cell routing, and output contention resolution are all performed in a distributed way so that the switch can be scaled up to a large size. The Abacus switch adopts a novel algorithm to resolve the contention of both multicast and unicast cells destined for the same output port (or output module). The switch can also handle multiple priority traffic by routing cells according to their priority levels. This paper describes a key ASIC chip for building the Abacus switch. The chip, called the ATM routing and concentration (ARC) chip, contains a two-dimensional array (3/spl times/32) of switch elements that are arranged in a cross-bar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8-/spl mu/m CMOS technology and tested to operate correctly at 240 MHz, Although the ARC chip was designed to handle the line rate at OC-3 (155 Mb/s), the Abacus switch can accommodate a much higher line rate at OC-12 (622 Mb/s) or OC-48 (2.5 Gb/s) by using a bit-sliced technique or distributing cells in a cyclic order to different inputs of the ARC chip. When the latter scheme is used, the cell sequence is retained at the output of the Abacus switch.