Surrounding Gate Research Articles

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English

Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO2) than Silicon Oxide (SiO2). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO2 than SiO2. It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO2 than SiO2.

A Study of Traditional and Surrounding Gate MOSFET using TCAD Simulations

A Study of Traditional and Surrounding Gate MOSFET using TCAD Simulations

Explicit continuous charge-based compact model for long channel heavily doped surrounding-gate MOSFETs incorporating interface traps and quantum effects

An explicit solution for long-channel surrounding-gate (SRG) MOSFETs is presented from intrinsic to heavily doped body including the effects of interface traps and fixed oxide charges. The solution is based on the core SRGMOSFETs model of the Unified Charge Control Model (UCCM) for heavily doped conditions. The UCCM model of highly doped SRGMOSFETs is derived to obtain the exact equivalent expression as in the undoped case. Taking advantage of the undoped explicit charge-based expression, the asymptotic limits for below threshold and above threshold have been redefined to include the effect of trap states for heavily doped cases. After solving the asymptotic limits, an explicit mobile charge expression is obtained which includes the trap state effects. The explicit mobile charge model shows very good agreement with respect to numerical simulation over practical terminal voltages, doping concentration, geometry effects, and trap state effects due to the fixed oxide charges and interface traps. Then, the drain current is obtained using the Pao–Sah's dual integral, which is expressed as a function of inversion charge densities at the source/drain ends. The drain current agreed well with the implicit solution and numerical simulation for all regions of operation without employing any empirical parameters. A comparison with previous explicit models has been conducted to verify the competency of the proposed model with the doping concentration of , as the proposed model has better advantages in terms of its simplicity and accuracy at a higher doping concentration.

Analytical modeling simulation and characterization of short channel Junctionless Accumulation Mode Surrounding Gate (JLAMSG) MOSFET for improved analog/RF performance

An analytical model for Junctionless Accumulation Mode Surrounding Gate (JLAMSG) MOSFET is developed using superposition technique. The model incorporates source/drain and channel depletion for an accurate analysis. The device parameter dependent electrostatic center potential, drain current (IDS) and subthreshold slope (SS) have been evaluated. The numerical simulation results using ATLAS-3D device simulator are in good agreement with the results obtained from the developed analytical model. A comparative assessment between Junctionless (JL) and Junctionless Accumulation Mode (JLAM) Surrounding Gate (SG) devices for analog/RF performance is also carried out. The superiority of JLAMSG MOSFET over Junctionless Surrounding Gate (JLSG) is discussed for Analog and RF application.

A New Device-Physics-Based Noise Margin/Logic Swing Model of Surrounding-Gate MOSFET Working on Subthreshold Logic Gate

In this paper, we present a device-physics-based noise margin (NM)/logic swing (LS) model of surrounding-gate (SRG) MOSFET working on subthreshold CMOS logic gates. Based on the device physics and equivalent transistor model, theoretical analysis of the main dc parameters, including LS and NM for SRG MOSFET operating in low-voltage condition, is revealed. It is shown that the device parameters, such as the thick silicon thickness $t_{\mathrm{ si}}$ , thick gate oxide thickness $t_{\mathrm{ ox}}$ , and short channel length $L_{g}$ , can severely degrade the LS and NM. On the contrary, both the small subthreshold slope $\eta $ and balanced transistor strength S induced by device parameters can suppress the NM and LS degradation efficiently. The required minimum supply voltage $V_{\mathrm{ dd,min}}$ for the subthreshold CMOS logic gate is derived by the criterion of the NM ≥ KT/ $q$ to ensure the correct logic gate operation. Being similar to DIBL, both NM and LS degraded by the device parameters can also be uniquely determined and controlled by the scaling factor according to scaling theory. Finally, considerations on the impact of process/voltage/temperature variation are also included for NM/LS behavior analysis.

Design and analysis of high sensitivity photosensor using Cylindrical Surrounding Gate MOSFET for low power applications

In this paper, a high sensitivity photosensor is proposed that utilizes the Zinc Oxide (metallic ZnO) which act as a transparent optical window over channel. High sensitivity is achieved by using Cylindrical Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (CSG MOSFET). On being exposed to light there is substantial increase in conductance and thereby change in the subthreshold current under exposure is utilized as a sensitivity parameter. Most of the Conventional FET based photosensors that are available utilizes threshold voltage as the parameter for sensitivity comparison but in this proposed sensor, under illumination change in the conductance resulting in variation of the subthreshold current is considered to be the sensitivity parameter. Performance comparison with Double Gate Metal Oxide Semiconductor Field Effect Transistor (DG MOSFET) in terms of sensitivity, threshold voltage and Ion/Ioff ratio is also done and observed results shows that CSG MOSFET is an ideal candidate for being used as a high sensitivity photosensor because in CSG MOSFET due to effective control of gate over channel low dark current, high sensitivity, low threshold voltage and high Ion/Ioff ratio can be achieved. Further impact of channel radius on responsivity (Re), quantum efficiency (Qe) and Ion/Ioff ratio is also studied for the proposed device.

Triple Material Surrounding Gate MOSFET for Suppression of SCES

Continuous downscaling of conventional MOSFETs suffers from various detrimental shortchannel effects (SCEs). A combination of novel device structures and material property improvement can overcome the SCEs in order to sustain the historical cadence of scaling. In this paper, a comprehensive analysis on the effect of downscaling in the performance of a novel gate-engineered Triple Material (TM) Surrounding Gate (SRG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is presented. With the help of device simulator Silvaco ATLAS, the effect of variation of the radius (R) and the channel length (L g ) on the surface potential, the Electric Field and the drain current is reported in order to provide an enticement for future theoretical studies and experimental researches of the critical aspects of the gate-engineered surrounding gate MOSFET. Results indicate that a trade-off between gate length L g and channel radius R is necessary to achieve higher immunity against SCEs with a lower OFF-state leakage current to find its usage in ultra low-power applications.

Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO2 than SiO2 in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, ION/IOFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO2, DIBL shows a reduction of 61.5% over SiO2. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO2 when compared to SiO2. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO2 based device. From the analysis, it is found that HfO2 will be a better alternative for the future nanoscale device.

Analytical modeling of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG)

SummaryThis paper presents physics based analytical model for center potential, electric field and subthreshold drain current of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM‐CSG). The expressions are derived from Poisson's equation in cylindrical co‐ordinate system based on parabolic potential approximation (PPA). The influence of technology parameter variations such as gate length, silicon pillar diameter and oxide thickness on electrical characteristics is studied in detail. Developed analytical model results are validated through the good agreement with simulated data obtained from ATLAS 3D simulator. Copyright © 2016 John Wiley & Sons, Ltd.

Impact of Inner Charge Control Gate on Cylindrical Surrounding Gate MOSFET for Improved Electrostatic Integrity and RF Performance

Impact of Inner Charge Control Gate on Cylindrical Surrounding Gate MOSFET for Improved Electrostatic Integrity and RF Performance

A Study of Traditional and Surrounding Gate MOSFET using TCAD Simulations

In this paper, Traditional and surrounding gate MOSFET are simulated using TCAD Silvaco and report the effect of multigate transistor. As the channel length of transistors is scaling down, a traditional MOSFET suffers from short channel effects and degrade the device performance. The different parameter such as threshold voltage, area, subthreshold slope, channel length modulation and leakage current are extracted for traditional and surrounding gate MOSFET. The parameters obtained from surrounding gate MOSFET is compared with a traditional MOSFET of the same dimension. The Results show that better performance was obtained for surrounding gate MOSFET. Its current drive capability is more as compared to traditional MOSFET .However, benefits of achieving superior performance with surrounding gate MOSFET reduces in terms of poor RF performance. Hence, this paper concludes that surrounding gate MOSFET have huge potential to be a promising contender to the traditional MOSFETs for making of future generation low-power high speed devices which could minimize the occupied area.

Triple Material Surrounding Gate (TMSG) Nanoscale Tunnel FET-Analytical Modeling and Simulation

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

Numerical modeling of Subthreshold region of junctionless double surrounding gate MOSFET (JLDSG)

In this paper, Numerical Model for Electric Potential, Subthreshold Current and Subthreshold Swing for Junctionless Double Surrounding Gate(JLDSG) MOSFEThas been developed using superposition method. The results have also been evaluated for different silicon film thickness, oxide film thickness and channel length. The numerical results so obtained are in good agreement with the simulated data. Also, the results of JLDSG MOSFET have been compared with the conventional Junctionless Surrounding Gate (JLSG) MOSFET and it is observed that JLDSG MOSFET has improved drain currents, transconductance, outputconductance, Transconductance Generation Factor (TGF) and Subthreshold Slope.

Modelling and simulation of subthreshold behaviour of cylindrical surrounding double gate MOSFET for enhanced electrostatic integrity

In this paper, a physics based model has been presented for the Cylindrical Surrounding Double Gate (CSDG) Nano-wire MOSFET. The analytical model is based on the solution of 2-D Poisson's equation in a cylindrical coordinate system using super-position technique. CSDG MOSFET is a cylindrical version of double gate MOSFET which offers maximum gate controllability over the channel. It consists of an inner gate and an outer gate. These gates render effective charge control inside the channel and also provide excellent immunity to short channel effects. Surface potential and electric field for inner and outer gate are derived. The impact of channel length on electrical characteristics of CSDG MOSFET is analysed and verified using ATLAS device simulator. The model is also extended for threshold voltage modelling using extrapolation method in strong inversion region. Drain current and transconductance are compared with conventional Cylindrical Surrounding Gate (CSG) MOSFET. The excellent electrical performance makes CSDG MOSFET promising candidates to extend CMOS scaling roadmap beyond CSG MOSFET.

Threshold voltage model of junctionless cylindrical surrounding gate MOSFETs including fringing field effects

2D Analytical model of the body center potential (BCP) in short channel junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs is developed using evanescent mode analysis (EMA). This model also incorporates the gate bias dependent inner and outer fringing capacitances due to the gate–source/drain fringing fields. The developed model provides results in good agreement with simulated results for variations of different physical parameters of JLCSG MOSFET viz. gate length, channel radius, doping concentration, and oxide thickness. Using the BCP, an analytical model for the threshold voltage has been derived and validated against results obtained from 3D device simulator.

A New Threshold Voltage and Drain Current Model for Lightly/Heavily Doped Surrounding Gate MOSFETs

A New Threshold Voltage and Drain Current Model for Lightly/Heavily Doped Surrounding Gate MOSFETs

Study on the On/Off Ratio of the Cylindrical Surrounding Gate CNT Transistor Using Nonequlibrium Green’s Function Approach

The effects of the nanotube diameter, channel length, gate dielectric constant and gate dielectric thickness on the on-off current ratio performance of cylindrical surrounding gate carbon nanotube transistors are studied using a ?-orbital tight binding simulation model. The focus is both on Schottky-barrier and the doped source-drain contact devices. The on current significantly improves with high-? gate dielectric, whereas off current decreases. The device on-off current ratio improves, from 6.33 × 105 to 1.5 × 106 for doped contact and from 0.61 × 104 to 1.22 × 104 for SB device with thinner gate oxide. Minimum leakage current increases with larger diameter tube but on-current has no significant improvement. I-V characteristics are independent of channel length when it is larger than 15 nm. Significant increase in off-current occurs due to scaling the channel length down to 10 nm but on-off ratio still exceeds 103. In all cases, on-off ratio is higher and the effect of scaling is more prominent for doped contact devices than SB contact devices.

Analytical Threshold Voltage Modeling of Surrounding Gate Silicon Nanowire Transistors with Different Geometries

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

Analog and RF Performance Analysis of a Junctionless Electrically Induced Source/Drain Extension Cylindrical Surround Gate (JLEJ-CSG) MOSFET

Junctionless (JL) transistors have recently been reported as strong candidate for the future technology nodes because of ease of manufacturing and improved performance over conventional MOSFETs. In this paper, the analog and RF performances of a JL transistor have been evaluated with metal gate structure having higher work function in the middle with two side gates of lower work function (electrically induced source/drain junctions, EJ). This triple metal gate JLEJ cylindrical surrounding gate (CSG) MOSFET provides better response in terms of intrinsic gain, transconductance generation factor, early voltage, unity gain transition frequency, maximum frequency of oscillation, etc. over single metal junctionless cylindrical surrounding gate (JLSM) transistors. However, the analog and RF performance metrics have been observed to be degraded because of quantum mechanical effects. The ION/IOFF ratio is improved by more than 105 times.