Supply Voltage Drop Research Articles

A 6T1C pixel circuit compensating for TFT electrical characteristics variations, voltage drop, and OLED degradation

A voltage-programmed pixel circuit based on low-temperature poly-silicon (LTPS) thin-film transistors (TFTs) is presented for active-matrix organic light-emitting diode (AMOLED) displays. The circuit consists of six p-type transistors and one capacitor (6T1C). During the extraction stage, the circuit extracts the driving TFT’s threshold voltage and the power supply voltage. During the data input stage, the circuit generates a charging voltage, which is associated with the driving TFT’s mobility and the OLED’s threshold voltage. Consequently, the pixel circuit, using only one capacitor, compensates not only for the TFT’s electrical characteristics variations, i.e., the threshold voltage variation and mobility variation, but also for the power supply voltage drop and the OLED degradation. The circuit simulation results reveal that the OLED current error rates (CERs) are lower than 5.09% when the threshold voltage varies by ±0.5V, lower than 3.61% when the mobility varies by ±30%, and lower than 9.16% when the voltage drop varies by −0.5V in the data voltage range.

A control with differential power-flow compensating of microgrid under symmetrical fault conditions

The load side failure of an independent microgrid will lead to an imbalance in power supply and demand and voltage drop in the fault area. The use of traditional reactive power compensation to achieve fault traversal in microgrids cannot effectively solve. This article proposes a differential power flow compensation control strategy based on micro source feeder impedance. Utilize micro source redundant power to increase active power output and compensate for the required power flow in the fault area. Calculate the power flow compensation coefficient based on the difference in feeder impedance, and dynamically adjust the reference value of power flow compensation according to the required power in the fault area. By rationalizing the distribution of fault flow, the transient power balance and voltage support in the fault area can be improved. To a certain extent, it enhances the fault resilience of the independent microgrid, and improves the working reliability during fault traversal. At the same time, it reduces the sharp increase in line losses caused by fault currents, and even endangers the security of network structures. The effectiveness of the strategy was verified through simulation and experiments.

Analysis of Power Supply Voltage Drop (IR-Drop) and Propagation Delay Using Folded Graphene Nano Ribbon Interconnect (F-GNR) Interconnect

Analysis of Power Supply Voltage Drop (IR-Drop) and Propagation Delay Using Folded Graphene Nano Ribbon Interconnect (F-GNR) Interconnect

AN ACCURACY IMPROVEMENT TECHNIQUE FOR ON-CHIP CURRENT SOURCES

A new design technique for accuracy improvement of on-chip reference current sources is proposed. A mathematical model has been developed describing the operation of the proposed technique. Based on the obtained equations, the variation of the reference current caused by the changes in operating conditions and process inaccuracies of the technological should not exceed 1…2%. The proposed technique has been implemented in the design of on-chip reference current source circuit in 14 nm FinFet technology. Spice simulations performed for the developed circuit show less than ± 5% variation of the reference current in the -40...1250C temperature range considering the process variations in ±3 sigma range. The circuit keeps that accuracy for the supply voltage drop up to 0.66 V.

Voltage Sensor Implementations for Remote Power Attacks on FPGAs

This article presents a study of two types of on-chip FPGA voltage sensors based on ring oscillators (ROs) and time-to-digital converter (TDCs), respectively. It has previously been shown that these sensors are often used to extract side-channel information from FPGAs without physical access. The performance of the sensors is evaluated in the presence of circuits that deliberately waste power, resulting in localized voltage drops. The effects of FPGA power supply features and sensor sensitivity in detecting voltage drops in an FPGA power distribution network (PDN) are evaluated for Xilinx Artix-7, Zynq 7000, and Zynq UltraScale+ FPGAs. We show that both sensor types are able to detect supply voltage drops, and that their measurements are consistent with each other. Our findings show that TDC-based sensors are more sensitive and can detect voltage drops that are shorter in duration, while RO sensors are easier to implement because calibration is not required. Furthermore, we present a new time-interleaved TDC design that sweeps the sensor phase. The new sensor generates data that can reconstruct voltage transients on the order of tens of picoseconds.

An Implantable Optogenetic Neuro-Stimulator SoC With Extended Optical Pulse-Width Enabled by Supply-Variation-Immune Cycled Light-Toggling Stimulation.

The design, development, and experimental validation of an inductively-powered four-channel optical neuro-stimulator system on a chip (SoC) with on-chip neural recording, temperature monitoring, signal processing, and bidirectional wireless data communication are presented. A biologically-inspired optical stimulation approach is employed that extends the limitations on the stimulation pulse-width and frequency (i.e., enabling wirelessly-powered optical stimulation at very low frequencies (e.g., 10 Hz)) while significantly reducing the required on-device storage capacitor size. The biological efficacy of the proposed approach is validated and compared with conventional stimulation through in vitro experiments. The stimulator's energy efficiency is enhanced by employing a high-gain (850 A/A) current amplifier/driver in each channel that steers up to 10 mA into the optical source with an excellent linearity ( 0.5LSB), while 1) yielding the lowest-in-literature required voltage headroom, and 2) being insensitive to large (up to 12%) supply voltage drops, which is ideal for battery-less implantable devices. Additionally, to maximize the percentage of the generated optical power that reaches the targeted cells (thus, further energy efficiency enhancement), inkjet printing is utilized to fabricate custom-designed optical μlenses that are placed directly on top of the silicon SoC to enhance the generated light's directivity by > 30×. An electrophysiological recording channel for real-time monitoring of the stimulation efficacy and a high-precision (0.1 °C resolution) temperature readout circuit for shutting off stimulation upon detection of an unsafe temperature increase are also integrated on the chip. Additionally, the SoC hosts an ASK receiver and an LSK transmitter for downlink and uplink wireless data communication, respectively. The SoC is fabricated in a standard 130 nm CMOS process and occupies 6 mm 2. Measurement results for different sensory and communication blocks are presented, as well as in vitro experimental validation results showing simultaneous optical stimulation, electrical recording, and calcium imaging.

Calculation of the components of the temperature measurement error by a resistance thermocouple of an installed unbalanced bridge

The article has devoted to solving an urgent problem related to the determination and calculation of the components of the temperature measurement error. A grain drying machine had selected as the object of research, in which the temperature of the grain at the exit from the machine is measured with the help of a Cu50 resistance thermocouple installed in an unbalanced bridge. It had found that the scale of the measuring device, calibrated in degrees Celsius, will have a nonlinearity error, which increases towards the end of the measurement range. For the Cu50 resistance thermocouple installed in the grain drying machine, when measuring the temperature in the range of 0 … 100 °C in absolute terms, the nonlinearity error was 0.3 mA, in relative terms - 4.4 %, which is quite large. The measurement error has calculated with a tolerance for the nominal resistance of the thermistor ± 0.1 Ohm, which in the given form was 0.5%. The resulting value indicates that this component will have an insignificant effect on the total measurement error. The measurement error due to the supply voltage drop by 0.2 V in relative form was 4.2 %. Thus, the voltage drops when using an unbalanced bridge will have a significant effect on the measurement result.

Analysis of the voltage drop of a drilling rig connected to a local energy network

The article discusses and analyzes the operation of an autonomous electrical complex of a drilling rig in an emergency mode, namely when the supply voltage drops. The concept of voltage drop is also described, a comparative characteristic of technical devices and methods of overcoming voltage drops, indicating the disadvantages and advantages, is given. Modeling of an autonomous electrical complex of a drilling rig is performed in the MATLAB Simulink software package with a description of the parameters of the main elements. The voltage drop is achieved by a sharp increase in the load power consumption, which in reality is achieved by the drilling rig head getting stuck in the hard layers of the earth’s surface. As a result, there are graphs of changes in the voltage value at the terminals of the electric motor of the drilling rig, depending on the magnitude of the load. Based on these graphs, we can conclude that with an increase in load, the autonomous system does not have its own reserves and power reserves (and according to regulatory documents, this margin is 20%) in order to overcome the voltage drop and return it to acceptable values for further uninterrupted operation. As a conclusion, we can say that today the only optimal option in terms of material costs and technical features is to connect a backup diesel generator connected in parallel to the main one and having a comparative power.

Study on A Fault Isolation Device in Low-voltage Network

A fault isolation device was designed in order to overcome the shortage of the traditional protective system. The corresponding circuit model was established and the character was analyzed when leakage occurred. Simulation study was carried out in this paper. The results show that a coupling voltage can be gotten which can drive the control system when leakage occurred. The adjustable capacity can be input reasonable by compare the supply voltage and voltage drop of the isolation device, thus the resonance parameters can be adjusted online and the electrical fault can be isolated effectively.

Supply Voltage and Temperature Dependence of Single-Event Transient in 28-nm FDSOI MOSFETs

Based on three-dimensional (3D) technology computer aided design (TCAD) simulations, the supply voltage and temperature dependence of single-event transient (SET) pulse width in 28-nm fully-depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated. FDSOI MOSFETs are symmetry devices with a superior control of the short channel effects (SCEs) and single-event effects (SEEs). Previous studies have suggested that the SET width is invariant when the temperature changes in FDSOI devices. Simulation results show that the SET pulse width increases as the supply voltage decreases. When the supply voltage is below 0.6 V, the SET pulse width increases sharply with the decrease of the supply voltage. The SET pulse width is not sensitive to temperature when the supply voltage is 1 V. However, when the supply voltage is 0.6 V or less, the SET pulse width exhibits an anti-temperature effect, and the anti-temperature effect is significantly enhanced as the supply voltage drops. Besides, the mechanism is analyzed from the aspects of saturation current and charge collection.

An implantable mixed-signal CMOS die for battery-powered in vivo blowfly neural recordings

A mixed-signal die containing two differential input amplifiers, a multiplexer and a 50 KSPS, 10-bit SAR ADC, has been designed and fabricated in a 0.35 μm CMOS process for in vivo neural recording from freely moving blowflies where power supplied voltage drops quickly due to the space/weight limited insufficient capacity of the battery. The designed neural amplifier has a 66 + dB gain, 0.13 Hz-5.3 KHz bandwidth and 0.39% THD. A 20% power supply voltage drop causes only a 3% change in amplifier gain and 0.9-bit resolution degrading for SAR ADC while the on-chip data modulation reduces the chip size, rendering the designed chip suitable for battery-powered applications. The fabricated die occupies 1.1 mm2 while consuming 238 μW, being suitable for implantable neural recordings from insects as small as a blowfly for electrophysiological studies of their sensorimotor control mechanisms. The functionality of the die has been validated by recording the signals from identified interneurons in the blowfly visual system.

Experimental study for the reproduction of sudden unintended acceleration incidents

A few cases of the sudden unintended acceleration have been reported over the last few years [1–11] and some of them seemed to be somewhat related to an electronic throttle control (ETC) system [11,12]. In this experimental study, efforts were made to reproduce the cases of sudden unintended acceleration possibly related to the ETC. Typically, an ETC of the engine is managed based on signals from airflow sensor, throttle position sensor and acceleration pedal sensor. With this typical sensor configuration in mind, these sensor signals were checked for noise levels. However, none of them showed any clear relationship with the sudden unintended acceleration mainly due to the robustness of the ETC logic software. As an alternative approach, supply voltage to an engine control unit (ECU) was tempered intentionally to observe any clues for the incidents. The observed results with the supply voltage drop and fluctuation tests were rather astonishing. The throttle valve position went all the way up to 100% for around one second when the battery voltage plunged down to 7V periodically despite that the acceleration pedal position was kept steady. As an effort to confirm the case, multiple tries were made systematically on a chassis dynamometer as well as on the test road. In this paper, detailed procedures and findings are reported accordingly.

Analysis of temperature dependent power supply voltage drop in graphene nanoribbon and Cu based power interconnects

In this paper, we propose a temperature dependent resistive model of multi layered graphene nanoribbon (MLGNR) and Cu based power interconnects. Using the proposed model, power supply voltage drop (IR-drop) analysis for 16 nm technology node is performed. The novelty in our work is that this is the first time a temperature dependent IR-Drop model for MLGNR and Cu interconnects is proposed. For a temperature range from 150 K to 450 K, the variation of resistance of MLGNR interconnect is ~2–5× times lesser than that of traditional copper based power interconnects. Our analysis shows that MLGNR based power interconnects can achieve ~1.5–3.5× reduction in IR-drop and ~1.5–3× reduction in propagation delay as compared with copper based interconnects for local, intermediate and global interconnects.

Investigating the Applicability of Graphene Nanoribbon as Signal and Power Interconnects for Nanometer Designs

In this work, we have investigated the applicability of graphene nanoribbon (GNR) as the interconnects for 16-nm ITRS technology node. GNR is proposed as the possible alternative to the traditional copper (Cu)-based interconnect systems in nanometer regime. In this paper, we have performed important studies on GNR for its applicability as power and signal interconnects. For the application of power interconnects, we have investigated the power supply voltage drop (IR drop) and simultaneous switching noise (SSN) in graphene-based interconnect system. We have performed crosstalk noise and overshoot/undershoot analyses for the application of signal interconnects. The results are compared with that of the traditional Cu-based interconnects. The results show that GNR is better than Cu as far as IR drop, SSN, gate oxide reliability and hot carrier reliability are concerned. Our investigation reveals that GNR can be better than the Cu interconnects from all aspects with a multilayer GNR structure. The present graphene-based interconnect technology needs to be advanced, so that the metal–graphene contact resistance is minimized and multilayer GNR structure with large number of graphene layers is supported.

DYNAMICS OF NON-UNIFORMITY LOADS OF AFC DRIVES

Abstract The length of armoured face conveyors currently used in hard coal mines most often ranges between 200 m and 300 m. The machines are equipped with a main and auxiliary drive. Asynchronous motors mounted in conveyor drives feature the capacity of several hundreds of kilowatts. The non-uniform distribution of loads onto individual drives is observed in practice. The numerical value of loads distribution onto the individual armoured face conveyor drives is represented by a drive load distribution factor. It is defined as a ratio between the load of an electric motor installed in a given drive and the total conveyor load. The article presents a physical armoured face conveyor model intended for examining dynamic phenomena influencing the load non-uniformity of drives. Motion in this physical model is described with the system of (4 · j + 5) non-linear ordinary differential quotations of the second order. A mathematical model is obtained by adding functions describing the interwork of sprocket drums with chains and functions approximating the mechanical characteristics of asynchronous motors powered by means of frequency inverters. A large number of computer simulations was performed using this model enabling to study the impact on the load non-uniformity of drives of such parameters as motor slip, motor supply voltage drop, variations in supply voltage frequency, differences in the gear ratio of transmissions and differentiation in the pitch of scraper chain links along the chain contour.

New Current-Scaling Pixel Circuit Compensating Non uniform Electrical Characteristics for Active Matrix Organic Light Emitting Diode

We have proposed and successfully fabricated a new serial current mirror pixel design for an active-matrix organic light-emitting diode which consists of four polycrystalline silicon thin-film transistors (poly-Si TFTs) and one capacitor. The non uniformity of OLED current (IOLED) due to the nature of a poly-Si TFT is considerably suppressed. Our experimental results show that the non uniformity of IOLED due to threshold voltage and mobility variation is around 7% whereas that of IOLED is about 25% in the conventional 2-TFT pixel. When supply voltage decreases from 10 V to 9.5 V, the non uniformity of OLED current is suppressed to 2.2% whereas that of OLED current is 35% in the 2-TFT pixel. The proposed pixel can successfully compensate the variation of the electrical characteristics of the poly-Si TFTs as well as provide uniform OLED current despite the supply voltage drop.

New voltage programming LTPS‐TFT pixel scaling down VTH variation for AMOLED display

A new voltage‐scaled compensation pixel which employs 3 p‐type poly‐Si TFTs and 2 capacitors without additional control line has been proposed and verified. The proposed pixel does not employ the VTH memorizing and cancellation, but scales down the inevitable VTH variation of poly‐Si TFT. Also the troublesome narrow input range of VDATA is increased and the VDD supply voltage drop is suppressed. In our experimental results, the OLED current error is successfully compensated by easily controlling the proposed voltage scaling effects.

Successive Pad Assignment for Minimizing Supply Voltage Drop

An efficient pad assignment methodology to minimize voltage drop on a power distribution network is proposed. A combination of successive pad assignment (SPA) with incremental matrix inversion (IMI) determines both location and number of power supply pads to satisfy drop voltage constraint. The SPA creates an equivalent resistance matrix which preserves both pad candidates and power consumption points as external ports so that topological modification due to connection or disconnection between voltage sources and candidate pads is consistently represented. By reusing sub-matrices of the equivalent matrix, the SPA greedily searches the next pad location that minimizes the worst drop voltage. Each time a candidate pad is added, the IMI reduces computational complexity significantly. Experimental results including a 400 pad problem show that the proposed procedures efficiently enumerate pad order in a practical time.

Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC

When subject to various power and substrate noise, configurable embedded memories in multimedia SoCs are importantly affected with pattern-dependant soft failures. This work investigates the effects of such failures on memory cells, arrays and circuit design. The ground bounce reduces the memory cell current more than the supply voltage drop or the substrate bias dip. A noise track-and-filter (NTAF) architecture, which is a self-timed architecture with specific layout patterns, is presented to provide the required timing relaxation, while minimizing the speed degradation. This NTAF method provides greater noise tolerance and design for manufacturing (DFM) capability. Configurable embedded SRAM and ROM in 0.18 μ m CMOS process are studied.

Continuously motor-synchronized ride-through capability for matrix-converter adjustable-speed drives

The ride-through capability of adjustable-speed drives has become an important issue due to its direct impact on production and revenue losses. Moreover, different industrial surveys have shown that voltage sags are the main cause of converter tripping. Disturbances such as swells, distortion, and impulses were found far less common and did not cause any tripping nor production losses. Matrix-converter (MC) drives are also prone to voltage sags, furthermore the lack of the DC-link capacitor renders them somehow more vulnerable. This paper presents a ride-through strategy for MC adjustable-speed drives. The strategy is based on the reduced speed/load approach for conventional drives and is capable of enforcing constant volts/hertz operation regardless of the supply voltage conditions by first regulating the modulation index of the matrix converter, which counteracts the supply voltage drop, and second by reducing the speed reference if required. This reduction seeks to maintain the maximum torque capability of the drive and not to reduce the motor load as in conventional drives. Hence, the proposed strategy is suitable for both variable and constant torque loads. Moreover, the converter never loses synchronization with the motor, so it is capable of immediate acceleration to its former speed after the disturbance disappears. The proposed strategy was experimentally verified under typical industry disturbances using a TMS320C32 DSP based system. Particularly, three-phase and single-phase sags varying from 10% to 60% were tested. Results obtained showed the effectiveness of the proposed strategy for MC adjustable-speed drives.