Superjunction Insulated Gate Bipolar Transistor Research Articles

Superjunction IGBT with split carrier storage layer

Abstract The Insulated Gate Bipolar Transistor (IGBT) is crucial in high-voltage applications due to its characteristics like breakdown voltage (BV) and on-state voltage VCE(sat). However, its slower turn-off time, attributed to hole mobility, restricts its frequency range. Techniques such as the carrier storage layer (CSL) and super-junction (SJ) structures aim to optimize BV and VCE(sat) through hole density and field distribution. Combining CSL and SJ offers advantages, yet challenges remain regarding E-field concentration. 
In this work, the split CSL concept introduces a solution by optimizing BV and Eoff through effective field distribution and hole extraction acceleration respectively while maintaining VCE(sat). Split CSL, which is divided into a high doping layer and a low doping layer, reduces the burden on the gate oxide by distributing the E-field evenly when in the off-state due to the difference in doping concentration. And during turn-off, hole current is concentrated on LDL, which has relatively low resistance, thereby accelerating hole extraction. Simulation-based results showcase improvements in the proposed structure's properties. The further optimization of high doping layer (HDL) and low doping layer (LDL) concentrations enhances the structure's performance. It is clear that the split CSL structure presents potential for advancing IGBT capabilities. The application of the split CSL structure resulted in significant improvements: the turn-off time was reduced by 32.4% and the breakdown voltage increased by 32.5 V compared to conventional CSL-SJ structures. These enhancements highlight the effectiveness of the split CSL design in optimizing the IGBT’s performance attribute.

Novel low loss dual-trench superjunction IGBT with semi-floating P-pillar

—In this paper, a novel dual-trench superjunction insulated gate bipolar transistor with semi-floating P-pillar (DTSFP-SJ-IGBT) is proposed and studied by simulation. The P-pillar of DTSFP-SJ-IGBT is semi-floating because only a portion is located below the trench gate, while a small part remains directly connected to the P-base. This small part P-pillar is depleted by the gate voltage in the on-state to enhance the carrier-storage effect, and provides an extraction hole path in the turning-off state to reduce the loss. The dual-trench structure results in a more uniform electric field distribution within the device while enhancing the carrier storage effect in the pillar regions. The simulation results show that at the same on-state voltage (VCE(sat)) of 1.30 V, the turn-off loss (Eoff) of the DTSFP-SJ-IGBT is 38.46 % lower than that of the superjunction IGBT with floating P-pillar (FP-SJ-IGBT), and 27.93 % lower than that of the recently reported superjunction IGBT with self-adaptive hole-extraction path (SAHE-SJ-IGBT). At the same Eoff of 1.00 mJ/cm2, the VCE(sat) of the DTSFP-SJ-IGBT is 44.70 % lower than that of the conventional superjunction IGBT (Con-SJ-IGBT).

Investigation on the carrier-storage super-junction IGBT: Characteristics, mechanism, and advantages

Operation mechanisms of the N-type Carrier-storage (N-CS) layer and Super-junction (SJ) pillar in Carrier-storage Super-junction Insulated Gate Bipolar Transistor (CS-SJBT) are clearly investigated in paper. It is pointed out that, under the effect of N-CS layer, Von of CS-SJBT is no more constrained by pillar doping as in CP-SJBTs, and the Von−Eoff contradiction along with pillar doping concentration in CP-SJBTs also no more exist in CS-SJBTs. Structural evolutions from CS-NDBT to CS-SJBT shows that, current conduction ability of SJ pillar and N-drift in CS-IGBTs are equivalent, and the role of SJ pillar locates in substantially reduced switching loss due to the two-dimensional electric field morphology in SJ pillar, which are supported by experimental contrasts. After these investigations, the conventional advantage of SJ in reducing on-state loss as in unipolar SJ-MOSFETs is diverted/extended to switching loss reduction ability in bipolar CS-SJBTs.

Actively controlled anode auxiliary gate super-junction insulated gate bipolar transistor with extremely low

When dealing with the super-junction insulated gate bipolar transistor (SJ-IGBT), due to its unipolar/bipolar mixed conduction mechanism, the approaches to improve its – are not exactly the same as for non-SJ IGBTs. In the pursuit of extremely low , a planar auxiliary anode gate SJ-IGBT (AAG-SJ-IGBT) is proposed based on a 650 V SJ-IGBT to realize a unipolar turn-off as observed in SJ-MOSFETs accompanied by fast switching and extremely low . The planar auxiliary anode gate provides similar effects but better feasibility than conventional trench ones. Sentaurus TCAD simulation results for the proposed AAG-SJ-IGBT indicate a 69% smaller and a 54% lower than the FP-SJ-IGBT, and its – is significantly optimized from cathode-improved SJ-IGBTs. The analysis of carrier and current density reveals the static and dynamic characteristics of the AAG-SJ-IGBT and the principle for excellent – trade-off.

Machine Learning Algorithm for Efficient Design of Separated Buffer Super-Junction IGBT

An improved structure for an Insulated Gate Bipolar Transistor (IGBT) with a separated buffer layer is presented in order to improve the trade-off between the turn-off loss (Eoff) and on-state voltage (Von). However, it is difficult to set efficient parameters due to the increase in the new buffer doping concentration variable. Therefore, a machine learning (ML) algorithm is proposed as a solution. Compared to the conventional Technology Computer-Aided Design (TCAD) simulation tool, it is demonstrated that incorporating the ML algorithm into the device analysis could make it possible to achieve high accuracy and significantly shorten the simulation time. Specifically, utilizing the ML algorithm could achieve coefficients of determination (R2) of Von and Eoff of 0.995 and 0.968, respectively. In addition, it enables the optimized design to fit the target characteristics. In this study, the structure proposed for the trade-off improvement was targeted to obtain the minimum Eoff at the same Von, especially by adjusting the concentration of the separated buffer. We could improve Eoff by 36.2% by optimizing the structure, which was expected to be improved by 24.7% using the ML approach. In another way, it is possible to inversely design four types of structures with characteristics close to the target characteristics (Eoff = 1.64 μJ, Von = 1.38 V). The proposed method of incorporating machine learning into device analysis is expected to be very strategic, especially for power electronics analysis (where the transistor size is comparatively large and requires significant computation). In summary, we improved the trade-off using a separated buffer, and ML enabled optimization and a more precise design, as well as reverse engineering.

A Superjunction Insulated Gate Bipolar Transistor with Embedded Self-biased N-Type Metal–Oxide–Semiconductor Field-Effect Transistor

A Superjunction Insulated Gate Bipolar Transistor with Embedded Self-biased N-Type Metal–Oxide–Semiconductor Field-Effect Transistor

650 V Super-Junction Insulated Gate Bipolar Transistor Based on 45 μm Ultrathin Wafer Technology

In this letter, 650 V generation I (thin) and generation II (ultrathin) super-junction insulated gate bipolar transistors (SJ-IGBT) based on deep trench etching and refilling processes are manufactured. It is worth mentioning that generation II is fabricated using 45 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\mu }\text{m}$ </tex-math></inline-formula> ultrathin wafer technology. Due to extra parasitic BJTs, both the thin and ultrathin SJ-IGBT have a larger base amplification factor, that the current density capability exceeds 650 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Compared with thin SJ-IGBT both at 650 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and at room temperature, the on- state voltage of the ultrathin SJ-IGBT could be decreased by about 160 mV, turn-off energy loss could be decreased by 22%. Furthermore, the ultrathin SJ-IGBT maintains a robust short circuit capability of no less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10~ {\mu }\text{s}$ </tex-math></inline-formula> under 400 V DC bus voltage.

Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers.

In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.

Low Switching Loss and EMI Noise IGBT With Self-Adaptive Hole-Extracting Path

A superjunction insulated gate bipolar transistor (SJ-IGBT) featuring a self-adaptive hole-extracting (SAHE) path is proposed and investigated by simulation. The SAHE path is formed by a narrow p-type mesa between the two trench gates. In the ON-state, the p-type mesa is depleted by the trench gates and the hole path is pinched off so as to maintain high injection efficiency, and thus a low ON-state voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) is achieved. During the turn-off period, the p-type mesa recovers into neutral region adaptively and then the hole-extracting path is opened, which helps decrease the turn-off loss ( E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) and suppress the dynamic avalanche. Moreover, at the initial turn-on stage with the SAHE path opening, the P-pillar in the proposed device is shorted to the emitter electrode rather than floating, which suppresses the negative capacitance effect. Therefore, compared with the SJ-IGBT with floating P-pillar, the SAHE SJ-IGBT not only achieves better V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> ON</sub> -E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> OFF</sub> tradeoff but also reduces the surge current by 23% at the turn-on stage and obtains better controllability on the turn-on dV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CE</sub> / dt and dI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> /dt characteristics, greatly decreasing the electromagnetic interference (EMI).

The design of a new heterogate superjunction insulated-gate bipolar transistor

A new heteromaterial planar-gate superjunction insulated-gate bipolar transistor (HG IGBT) is proposed herein. It consists of stepped gate oxides with thickness of 50 nm, 100 nm, and 150 nm. The gate of the proposed structure is constructed using two materials with different workfunction in a triple-segment polygate configuration, connected via metal on the top. The first and last segment consist of the higher-workfunction material ( $$P^{+}$$ poly) while the mid segment is formed by a lower-workfunction material ( $$N^{+}$$ poly). The first $$P^{+}$$ poly gate near the emitter with a thin (50 nm) oxide layer enables better control over charge carriers in the channel. In addition, the last $$P^{+}$$ poly gate with a thicker (150 nm) oxide layer results in a reduction of the gate-to-collector capacitance. Technology computer-aided design (TCAD) simulation results show that the proposed device offers a 23%, 58%, and 22% reduction in the area-specific on resistance ( $$R_{{\mathrm {on}}} \cdot A$$ ), switching delay, and turn-off time, respectively. Additionally, the device exhibits a 44.4% improvement in the peak transconductance for given breakdown voltage (BV). Furthermore, the off-state energy loss and on-state voltage drop are reduced by 38% and 22%, respectively. It is also observed that the proposed device offers an improved figure of merit (FOM) as compared with the conventional structure.

Superjunction IGBT With Conductivity Modulation Actively Controlled by Two Separate Driving Signals

A dual-gate superjunction insulated gate bipolar transistor (IGBT) (DG-SJ-IGBT) is proposed and studied with numerical TCAD simulations. The new structure utilizes the superjunction structure as a controlling port for the strength of conductivity modulation inside the IGBT, so that a low ${V}_{\text {ON}}$ is obtained by a strong conductivity modulation during ON-state and a near-unipolar turn-off is achieved by removing the minority carriers before the turn-off event. For this purpose, the p-pillar in the DG-SJ-IGBT is connected to the p-body using a built-in p-channel MOSFET. The primary gate and the auxiliary gate (i.e., gate of p-MOSFET) are controlled by two separate driving signals. In the IGBT’s ON-state, the p-MOSFET disconnects the p-pillar, enabling full conductivity-modulated bipolar conduction and a consequent low ${V}_{\text {ON}}$ . As a well-known issue, conductivity modulation is accompanied by significant additional turn-off loss ( ${E}_{\text {OFF}}$ ). To overcome this issue, the DG-SJ-IGBT takes advantage of the p-pillar which extends through the entire drift region. Before the IGBT’s turn-off event, the p-MOSFET electrically grounds the p-pillar to the p-body. The grounded p-pillar serves as a hole extractor, suppresses the minority carrier density throughout the depth of the drift region, and brings the device into a near-unipolar conduction mode. Thus, a near-unipolar turn-off can be obtained, resulting in a low ${E}_{\text {OFF}}$ .

Carrier‐storage‐enhanced superjunction IGBT with n‐Si and p‐3C‐SiC pillars

A carrier-storage-enhanced superjunction (SJ) insulated gate bipolar transistor (IGBT) with n-Si and p-3C-SiC pillars (Si/SiC SJ IGBT) is studied. At the on-state, the n-Si/p-SiC heterojunction acts as a barrier for holes in the n-Si pillar, which helps to enhance the carrier-storage effect in the n-Si pillar and improves the tradeoff between turn-off loss ( E off ) and on-state voltage drop ( V CE(sat) ). It is found by simulations that V CE(sat) of the Si/SiC SJ IGBT can be 0.35 V lower than that of the conventional SJ IGBT with the same breakdown voltage ( V B = 1450 V). Under E off = 5 mJ/cm 2 , V CE(sat) of the Si/SiC SJ IGBT is 1.22 V, which is 0.30 and 0.81 V lower than V CE(sat) of the conventional SJ IGBT and the field stop IGBT, respectively.

Simulation Study of a Low ON-State Voltage Superjunction IGBT With Self-Biased PMOS

In this brief, a novel superjunction (SJ)-insulated-gate bipolar transistor (SJ-IGBT) is proposed and investigated by simulation, where a floating N-base region on the P-pillar region is introduced to form a self-biased PMOS. In the on-state, the PMOS can increase the hole quasi-Fermi potential of the P-pillar region, enhancing the carrier-storage effect in the N-pillar and P-pillar regions and reducing the on-state voltage consequently. In the turn-off transient, because the PMOS can be automatically turned on as a consequence of the potential rise of the P-pillar region with hole accumulation, the proposed SJ-IGBT can be rapidly turned off. The results from TCAD simulation reveal that the on-state voltage of the proposed SJ-IGBT is 46.7% lower than that of the conventional SJ-IGBT with P-pillar shorted with cathode (SJ-IGBT-A) and nearly equivalent to that of the conventional SJ-IGBT with gate on the P-pillar (SJ-IGBT-B). In addition, the off-state breakdown voltage of the proposed SJ-IGBT can roughly keep an identical value with that of SJ-IGBT-A and is 25% higher than that of SJ-IGBT-B. In addition, with the same VON of 1.16 V, the turn-off energy loss of the proposed device is 1.2 mJ/cm2, which is 94.7% lower than that of SJ-IGBT-A and 20% lower than that of SJ-IGBT-B.

Turn-OFF Transient Analysis of Superjunction IGBT

A turn-OFF transient analysis of the superjunction (SJ) insulated-gate bipolar transistor (IGBT) based on an analytical model as a function of structural parameters is presented in this paper. The physical phenomenon dependent on the doping density of the n-/p-pillar of the SJ IGBT could be explained using the analytical model to predict the static and transient characteristics. From this model, tradeoff between turn-OFF loss and ON-state voltage has been obtained, as verified by the TCAD simulations with a good agreement.

Superjunction Power Devices, History, Development, and Future Prospects

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs).

An Ultralow Loss Superjunction Reverse Blocking Insulated-Gate Bipolar Transistor With Shorted-Collector Trench

A novel superjunction (SJ) reverse-blocking (RB) insulated gate bipolar transistor (IGBT) is proposed and investigated for the first time. The device features a shorted collector trench (SCT) at the bottom, an SJ structure in the drift region, and an N1-layer as well as N2-layer at the bottom and top side of N-pillar, respectively. First, the SCT combined with the N2 enables the SJ RB-IGBT to sustain a high reverse breakdown voltage (BV $_{\textit {R}}$ ). The SCT assists in depleting the N1 in the reverse blocking state, enabling a high BV $_{\textit {R}}$ under the condition of a high N1 doping that is required to maintain a high forward breakdown voltage (BV $_{\textit {F}}$ ). The N2 acts as a field-stop layer in the reverse blocking state. Second, unlike the conventional SJ IGBT, the SJ RB-IGBT maintains bipolar conducting mode in the ON-state even with high N/P pillar doping of $6 \times 10^{15}$ cm $^{\mathrm {-3}}$ , due to carrier store effect induced by N2. Thus, a low ON-state voltage ( $\text{V}_{\mathrm{\scriptscriptstyle ON}}$ ) is obtained. Third, the SJ junction extracts the plasma into separate pillars during turn OFF, enabling a fast turn-OFF speed that is comparable with unipolar devices. The SJ RB-IGBT realizes bidirectional blocking capability >1200V and turn-OFF loss 80% lower than that of the state-of-the-art RB-IGBT.

A novel high performance TFS SJ IGBT with a buried oxide layer

A novel high performance trench field stop (TFS) superjunction (SJ) insulated gate bipolar transistor (IGBT) with a buried oxide (BO) layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT (Conv-SJ), the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop (Vce(on)) and an improved tradeoff between Vce(on) and turn-off loss (Eoff), with no breakdown voltage (BV) degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5 μm and Nn = Np = 3 × 10 cm−3, the Vce(on) and Eoff of the proposed structure are 1.08 V and 2.81 mJ/cm2 with the collector doping concentration Nc = 1 × 1018 cm−3 and 1.12 V and 1.73 mJ/cm2 with Nc = 5 × 1017 cm−3, respectively. However, with the same device parameters, the Vce(on) and Eoff for the Conv-SJ are 1.81 V and 2.88 mJ/cm2 with Nc = 1 × 1018 cm−3 and 1.98 V and 2.82 mJ/cm2 with Nc = 5 × 10 cm−3, respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.

A simulation study on a novel trench SJIGBT

An overall analysis of the trench superjunction insulated gate bipolar transistor (SJ IGBT) is presented and a detailed comparison between a trench SJ IGBT and a trench field stop IGBT is made by simulating with Sentaurus TCAD. More specifically, simulation results show that the trench SJ IGBT exhibits a breakdown voltage that is raised by 100 V while the on-state voltage is reduced by 0.2 V. At the same time, the turn-off loss is decreased by 50%. The effect of charge imbalance on the static and dynamic characteristics of the trench SJ IGBT is studied, and the trade-off between parameters and their sensitivity versus charge imbalance is discussed.

Towards Achieving the Soft-Punch-Through Superjunction Insulated-Gate Bipolar Transistor Breakdown Capability

The termination design of superjunction (SJ) structures has always been a conceptual and technological challenge. In this letter, we propose new, optimized, elegant, and cost-efficient solutions toward the realization of the first 1.2-kV rated SJ insulated-gate bipolar transistor. The design is based on the utilization of existing layers in the device fabrication line, hence resulting in no extra complexity or cost increase. The proposed design effectiveness is confirmed through extensive numerical simulations.

The Soft $\hbox{Punchthrough}+$ Superjunction Insulated Gate Bipolar Transistor: A High Speed Structure With Enhanced Electron Injection

The aim of this paper is to demonstrate the application of the superjunction (SJ) design in an insulated gate bipolar transistor (IGBT). Bipolar conduction is present and enhanced at the cathode side of the device, while the p-pillars collect the plasma deep from the anode side, thus significantly enhancing its turn-off speed. The disconnected soft punchthrough + (SPT+) SJ IGBT is similar to the SJ IGBT, which we have previously reported, but the drift region pillars do not extend up to the cathode contact. Instead, the upper part of this device is similar to the SPT+ IGBT, i.e., it features an n+ injector around the p-well and the n-drift region that is lightly doped. The improvement in the overall performance is impressive (25% lower ON-state losses and 30% lower switching losses) and can indeed justify the technology cost associated with the SJ technology. We also demonstrate how this technology can be used to form a snapback-free reverse conducting IGBT.